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2013 IEEE 31st VLSI Test Symposium (VTS) (1996)
Princeton, NJ
Apr. 28, 1996 to May 1, 1996
ISBN: 0-8186-7304-4
TABLE OF CONTENTS

Foreword (PDF)

pp. xiii

Reviewers (PDF)

pp. xix
Keynote Address
Invited Talk
Session 1: Design for Testability

Test point insertion based on path tracing (Abstract)

N.A. Touba , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 2

Design of a fast, easily testable ALU (Abstract)

J.P. Hayes , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.D. Blanton , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 9

A self-driven test structure for pseudorandom testing of non-scan sequential circuits (Abstract)

F. Muradali , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
J. Rajski , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 17

Scan insertion criteria for low design impact (Abstract)

F. Corno , Central R&D Dept., Italy
M. Sonza Reorda , Central R&D Dept., Italy
D. Medina , Central R&D Dept., Italy
S. Barbagallo , Central R&D Dept., Italy
M. Lobetti Bodoni , Central R&D Dept., Italy
P. Prinetto , Central R&D Dept., Italy
pp. 26

Segment delay faults: a new fault model (Abstract)

J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
K. Heragu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
V.D. Agrawal , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 32
Session 2: Testability of Analog Circuits

Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design (Abstract)

D. Vazquez , Centro Nacional de Microelectron., Seville Univ., Spain
A. Rueda , Centro Nacional de Microelectron., Seville Univ., Spain
J.L. Huertas , Centro Nacional de Microelectron., Seville Univ., Spain
pp. 42

Optimization of analog IC test structures (Abstract)

A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E. Felt , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 48

The multi-configuration: A DFT technique for analog circuits (Abstract)

Y. Bertrand , Lab. d'Inf., Robotique et Microelectronique, Montpellier, France
F. Azais , Lab. d'Inf., Robotique et Microelectronique, Montpellier, France
M. Renovell , Lab. d'Inf., Robotique et Microelectronique, Montpellier, France
pp. 54

A new digital test approach for analog-to-digital converter testing (Abstract)

M. Ehsanian , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
K. Arabi , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 60

Iterative test-point selection for analog circuits (Abstract)

J. Van Spaandonk , Eindhoven Univ. of Technol., Netherlands
T.A.M. Kevenaar , Eindhoven Univ. of Technol., Netherlands
pp. 66
Session 3: Synthesis for Testability

H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads (Abstract)

S. Dey , NEC Res. Inst., Princeton, NJ, USA
S. Bhattacharya , NEC Res. Inst., Princeton, NJ, USA
pp. 74

Standard and ROM-based synthesis of FSMs with control flow checking capabilities (Abstract)

R. Rochet , Inst. Nat. Polytech. de Grenoble, France
X. Wendling , Inst. Nat. Polytech. de Grenoble, France
R. Leveugle , Inst. Nat. Polytech. de Grenoble, France
pp. 81

Synthesis-for-scan and scan chain ordering (Abstract)

R.B. Norwood , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 87

Synchronization of large sequential circuits by partial reset (Abstract)

Y. Lu , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 93

Development of test programs in a virtual test environment (Abstract)

W. Wolz , Inst. of Comput.-Aided Circuit Design, Erlangen-Nurnberg Univ., Germany
M. Miegler , Inst. of Comput.-Aided Circuit Design, Erlangen-Nurnberg Univ., Germany
pp. 99
Session 4: IDDQ Testing

On estimating bounds of the quiescent current for I/sub DDQ/ testin (Abstract)

A. Ferre , Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras , Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 106

Current signatures [VLSI circuit testing] (Abstract)

W. Maly , Carnegie Mellon Univ., Pittsburgh, PA, USA
A.E. Gattiker , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 112

A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs (Abstract)

S.P. Athan , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
S.A. Al-Arian , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
D.L. Landis , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 118

Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring (Abstract)

M. Nicolaidis , Univ. Politecnica de Catalunya, Barcelona, Spain
S. Manich , Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras , Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 124

Improvement of SRAM-based failure analysis using calibrated Iddq testing (Abstract)

H. Balachandran , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
D.M.H. Walker , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 130
Session 5: On-Line Testing

Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems (Abstract)

E.S. Sogomonyan , Inst. of Control Sci., Acad. of Sci., Moscow, Russia
M. Gossel , Inst. of Control Sci., Acad. of Sci., Moscow, Russia
pp. 138

Embedded two-rail checkers with on-line testing ability (Abstract)

C. Metra , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
B. Ricco , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 145

An asynchronous totally self-checking two-rail code error indicator (Abstract)

P. Kostarakis , Inst. of Inf., NCSR "Demokritos", Athens, Greece
A. Paschalis , Inst. of Inf., NCSR "Demokritos", Athens, Greece
D. Gizopoulos , Inst. of Inf., NCSR "Demokritos", Athens, Greece
N. Gaitanis , Inst. of Inf., NCSR "Demokritos", Athens, Greece
pp. 151

A self-checking ALU design with efficient codes (Abstract)

S.S. Gorshe , NEC America Inc., Hillsboro, OR, USA
B. Bose , NEC America Inc., Hillsboro, OR, USA
pp. 157

Self-dual parity checking-A new method for on-line testing (Abstract)

Vl.V. Saposhnikov , St. Petersburg State Univ., Russia
A. Dmitriev , St. Petersburg State Univ., Russia
V.V. Saposhnikov , St. Petersburg State Univ., Russia
M. Goessel , St. Petersburg State Univ., Russia
pp. 162

Safety computations in integrated circuits (Abstract)

J.-L. Dufour , RAMS Dept., Matra Transp. Int., Montrouge, France
pp. 169
Session 6: Fault Diagnosis and Dictionaries

Full fault dictionary storage based on labeled tree encoding (Abstract)

I. Hartanto , Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA
W.K. Fuchs , Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA
V. Boppana , Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA
pp. 174

Improving the accuracy of diagnostics provided by fault dictionaries (Abstract)

W.R. Simpson , ARINC Res. Corp., Annapolis, MD, USA
J.W. Sheppard , ARINC Res. Corp., Annapolis, MD, USA
pp. 180

A sampling technique for diagnostic fault simulation (Abstract)

S. Chakravarty , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
pp. 192

Dynamic diagnosis of sequential circuits based on stuck-at faults (Abstract)

W. Kent Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
S. Venkataraman , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
I. Hartanto , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 198

On the diagnosis of programmable interconnect systems: Theory and application (Abstract)

W.K. Huang , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
X.T. Chen , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 204
Panel Session 1:
Panel Session 2
Session 7: Sequential Circuit Testing

Automatic test generation using genetically-engineered distinguishing sequences (Abstract)

M.S. Hsiao , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
E.M. Rudnick , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 216

Increasing testability by clock transformation (getting rid of those darn states) (Abstract)

M. Abramovici , Sun Microsyst., Menlo Park, CA, USA
D.E. Long , Sun Microsyst., Menlo Park, CA, USA
K.B. Rajan , Sun Microsyst., Menlo Park, CA, USA
pp. 224

An analysis of fault partitioning algorithms for fault partitioned ATPG (Abstract)

R.H. Klenke , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.H. Aylor , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.M. Wolf , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 231

On the (non-)resetability of synchronous sequential circuits (Abstract)

B. Becker , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
B. Stenner , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
M. Keim , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 240

Initialization of sequential circuits and its application to ATPG (Abstract)

J.A. Wehbeh , MIPS Technol. Inc., Mountain View, CA, USA
D.G. Saab , MIPS Technol. Inc., Mountain View, CA, USA
pp. 246
Session 8: Multi-Chip Modules and Memory Testing

Faulty chip identification in a multi chip module system (Abstract)

M.J. Chung , Nat. Res. Council, US Army Res. Labs., Fort Monmouth, NJ, USA
G.T. Michael , Nat. Res. Council, US Army Res. Labs., Fort Monmouth, NJ, USA
Wei Su , Nat. Res. Council, US Army Res. Labs., Fort Monmouth, NJ, USA
T.R. Damarla , Nat. Res. Council, US Army Res. Labs., Fort Monmouth, NJ, USA
pp. 254

Low-cost diagnosis of defects in MCM substrate interconnections (Abstract)

M. Swaminathan , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
B.C. Kim , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 260

March LR: a test for realistic linked faults (Abstract)

A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
V.G. Mikitjuk , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
G.N. Gaydadjiev , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
V.N. Yarmolik , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 272

Design of a fault tolerant 100 Gbits solid-state mass memory for satellites (Abstract)

F. Simon , Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, Franc
J.Y. Le Gall , Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, Franc
M.P. Kluth , Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, Franc
E. Muller , Autom. & Intelligent Syst. Unit., Alcatel Alsthom Recherche, Marcoussis, Franc
pp. 281
Session 9: Delay Fault Testing

On minimizing the number of test points needed to achieve complete robust path delay fault testability (Abstract)

I. Pomeranz , Avant Corp., Research Triangle Park, NC, USA
U. Sparmann , Avant Corp., Research Triangle Park, NC, USA
P. Uppaluri , Avant Corp., Research Triangle Park, NC, USA
pp. 288

A new test pattern generation method for delay fault testing (Abstract)

C. Fagot , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Girard , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Cremoux , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 296

On completely robust path delay fault testable realization of logic functions (Abstract)

V.A. Vardanian , Inst. of Inf. & Autom. Problems, Acad. of Sci., Yerevan, Armenia
pp. 302

An algebraic method for delay fault testing (Abstract)

S. Crepaux-Motte , Lab. d'Autom., Inst. Nat. Polytech. de Grenoble, St.-Martin-d'Heres, France
R. David , Lab. d'Autom., Inst. Nat. Polytech. de Grenoble, St.-Martin-d'Heres, France
M. Jacomino , Lab. d'Autom., Inst. Nat. Polytech. de Grenoble, St.-Martin-d'Heres, France
pp. 308

A diagnosability metric for parametric path delay faults (Abstract)

M. Sivaraman , Carnegie Mellon Univ., Pittsburgh, PA, USA
A.J. Strojwas , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 316
Session 10: Non-Traditional Testing

Testing "untestable" faults in three-state circuits (Abstract)

P. Wohl , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
M. Graf , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
J. Waicukauski , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
pp. 324

Quantitative analysis of very-low-voltage testing (Abstract)

J.T.-Y. Chang , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 332

Bridging fault coverage improvement by power supply control (Abstract)

P. Huc , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Y. Bertrand , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
M. Renovell , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 338

Optimal voltage testing for physically-based faults (Abstract)

Yuyun Liao , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
D.M.H. Walker , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 344

Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages (Abstract)

P. Pant , Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Georgia Inst. of Technol., Atlanta, GA, USA
J.A. Abraham , Georgia Inst. of Technol., Atlanta, GA, USA
R. Jayabharathi , Georgia Inst. of Technol., Atlanta, GA, USA
pp. 354
Panel Session 3:
Panel Session 4:
Panel Session 5:
Session 11: Advances in Built-In Self-Test

Design and performance of CMOS TSPC cells for high speed pseudo random testing (Abstract)

B. Kaminska , Ecole Polytech. de Montreal, Que., Canada
S. Rochon , Ecole Polytech. de Montreal, Que., Canada
M. Soufi , Ecole Polytech. de Montreal, Que., Canada
Y. Savaria , Ecole Polytech. de Montreal, Que., Canada
pp. 368

Generating deterministic unordered test patterns with counters (Abstract)

D. Kagaris , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 374

Test response compaction using arithmetic functions (Abstract)

A.P. Stroele , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 380

Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) (Abstract)

C. Stroud , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
M. Abramovici , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
S. Konala , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
Ping Chen , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
pp. 387

Applying two-pattern tests using scan-mapping (Abstract)

E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
N.A. Touba , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 393
Session 12: Fault Modeling and Defect Coverage

Consistently dominant fault model for tristate buffer nets (Abstract)

T.J. Powell , Texas Instrum. Inc., Dallas, TX, USA
pp. 400

Fault characterization of standard cell libraries using inductive contamination (Abstract)

N. Tiday , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J. Khare , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 405

A fault model for switch-level simulation of gate-to-drain shorts (Abstract)

P. Dahlgren , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
P. Liden , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
pp. 414

An unexpected factor in testing for CMOS opens: the die surface (Abstract)

H. Konuk , California Design Center, Hewlett-Packard Co., CA, USA
F.J. Ferguson , California Design Center, Hewlett-Packard Co., CA, USA
pp. 422

On the effects of test compaction on defect coverage (Abstract)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S. Kajihara , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 430
Session 13: Fault Simulation and Test Generation

ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator (Abstract)

M.B. Amin , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
B. Vinnakota , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 438

Testing trees for multiple faults (Abstract)

C. Tobon , Dept. of Comput. Eng., Patras Univ., Greece
A. Vergis , Dept. of Comput. Eng., Patras Univ., Greece
pp. 444

An approach for testing programmable/configurable field programmable gate arrays (Abstract)

F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
W.K. Huang , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 450

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits (Abstract)

J.H. Patel , Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
I.N. Hajj , Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
T. Lee , Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
E.M. Rudnick , Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
pp. 456

Isomorph-redundancy in sequential circuits (Abstract)

B.B. Bhattacharya , Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
U.K. Bhattacharya , Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
D.K. Das , Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
pp. 463
Session 14: Mixed-Signal Test Techniques

A novel test generation approach for parametric faults in linear analog circuits (Abstract)

J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
H.H. Zheng , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
A. Balivada , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 470

Oscillation-test strategy for analog and mixed-signal integrated circuits (Abstract)

K. Arabi , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 476

Monitoring power dissipation for fault detection (Abstract)

B. Vinnakota , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 483

Implicit functional testing for analog circuits (Abstract)

Chen-Yang Pan , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 489

Analog circuit simulation and troubleshooting with FLAMES (Abstract)

F. Novak , TIMA Lab., Grenoble, France
M. Manzouki , TIMA Lab., Grenoble, France
A. Biassizo , TIMA Lab., Grenoble, France
F. Mohamed , TIMA Lab., Grenoble, France
pp. 495
Panel Session 6:
Panel Session 7:

Board-Level BIST (PDF)

pp. 504
Panel Session 8:

Author Index (PDF)

pp. 508
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