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2013 IEEE 31st VLSI Test Symposium (VTS) (1996)
Princeton, NJ
Apr. 28, 1996 to May 1, 1996
ISBN: 0-8186-7304-4
pp: 456
J.H. Patel , Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
I.N. Hajj , Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
T. Lee , Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
E.M. Rudnick , Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
ABSTRACT
An efficient automatic test pattern generator for I/sub DDQ/ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. An adaptive genetic algorithm (GA) is used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that GA-based test generators are very well suited for generating compact test sets for I/sub DDQ/ testing of bridging faults.
INDEX TERMS
CMOS digital integrated circuits; VLSI; automatic testing; genetic algorithms; integrated circuit testing; fault location; logic testing; GA-based test generators; ATPG; bridging faults; CMOS VLSI circuits; automatic test pattern generator; I/sub DDQ/ current testing; CMOS digital circuits; two-line bridging fault set; adaptive genetic algorithm; compact test set generation
CITATION
J.H. Patel, I.N. Hajj, T. Lee, E.M. Rudnick, "Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 456, 1996, doi:10.1109/VTEST.1996.510893
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