2013 IEEE 31st VLSI Test Symposium (VTS) (1996)
Apr. 28, 1996 to May 1, 1996
M.S. Hsiao , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
E.M. Rudnick , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test generation process. A two-phase algorithm is used during test generation. The first phase activates the target fault, and the second phase propagates the fault effects (FE's) from the flip-flops with assistance from the distinguishing sequences. This strategy improves the propagation of FE's to the primary outputs, and the overall fault coverage is greatly increased. In our new test generator, DIGATE, genetic algorithms are used to derive both activating and distinguishing sequences during test generation. Our results show very high fault coverages for the ISCAS89 sequential benchmark circuits and several synthesized circuits.
fault diagnosis; logic testing; sequential circuits; automatic testing; genetic algorithms; sequences; automatic test generation; distinguishing sequence; sequential circuit; two-phase algorithm; fault effects; flip-flops; DIGATE; genetic algorithm
M.S. Hsiao, E.M. Rudnick, J.H. Patel, "Automatic test generation using genetically-engineered distinguishing sequences", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 216, 1996, doi:10.1109/VTEST.1996.510860