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2013 IEEE 31st VLSI Test Symposium (VTS) (1995)
Princeton, New Jersey
Apr. 30, 1995 to May 3, 1995
ISBN: 0-8186-7000-2
TABLE OF CONTENTS

Foreword (PDF)

pp. xii

Reviewers (PDF)

pp. xvi
Session 1: Advanced Test Pattern Generation Methods

Identifying sequentially untestable faults using illegal states (Abstract)

D.E. Long , AT&T Bell Labs., Murray Hill, NJ, USA
M.A. Iyer , AT&T Bell Labs., Murray Hill, NJ, USA
M. Abramovici , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 0004

High-level test generation using physically-induced faults (Abstract)

M.C. Hansen , Advanced Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Advanced Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 0020

A portable ATPG tool for parallel and distributed systems (Abstract)

F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Rebaudengo , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M.S. Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
E. Veiluva , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 0029

Testing combinational iterative logic arrays for realistic faults (Abstract)

D. Gizopoulos , Inst. of Informatics & Telecommun., NCSR Demokritos, Attiki, Greece
D. Nikolos , Inst. of Informatics & Telecommun., NCSR Demokritos, Attiki, Greece
A. Paschalis , Inst. of Informatics & Telecommun., NCSR Demokritos, Attiki, Greece
pp. 0035
Session 2: Mixed-Signal Circuit Test

Verification of transient response of linear analog circuits (Abstract)

A. Balivada , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Y. Hoskote , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 0042

A solution for the on-line test of analog ladder filters (Abstract)

D. Vazquez , Dpto. de Diseno Analogico, Univ. de Sevilla, Spain
A. Rueda , Dpto. de Diseno Analogico, Univ. de Sevilla, Spain
J.L. Huertas , Dpto. de Diseno Analogico, Univ. de Sevilla, Spain
pp. 0048

Frequency-based BIST for analog circuit testing (Abstract)

S. Khaled , Ecole Polytech., Montreal, Que., Canada
B. Kaminska , Ecole Polytech., Montreal, Que., Canada
B. Courtois , Ecole Polytech., Montreal, Que., Canada
M. Lubaszewski , Ecole Polytech., Montreal, Que., Canada
pp. 0054

A low cost 100 MHz analog test bus (Abstract)

S. Sunter , Telecom Microelectron. Centre, Northern Telecom Electron. Ltd., Nepean, Ont., Canada
pp. 0060

Self-test in a VCM driver chip (Abstract)

L. Sebaa , Western Digital Corp., Irvine, CA, USA
N. Gardner , Western Digital Corp., Irvine, CA, USA
R. Neidorff , Western Digital Corp., Irvine, CA, USA
R. Valley , Western Digital Corp., Irvine, CA, USA
pp. 0066
Session 3: Defect Coverage and Test Quality

On the decline of testing efficiency as fault coverage approaches 100% (Abstract)

L.-C. Wang , Texas Univ., Austin, TX, USA
P.R. Mercer , Texas Univ., Austin, TX, USA
S.W. Kao , Texas Univ., Austin, TX, USA
T.W. Williams , Texas Univ., Austin, TX, USA
pp. 0074

Cyclic stress tests for full scan circuits (Abstract)

V. Dabholkar , State Univ. of New York, Buffalo, NY, USA
S. Chakravarty , State Univ. of New York, Buffalo, NY, USA
J. Najm , State Univ. of New York, Buffalo, NY, USA
J. Patel , State Univ. of New York, Buffalo, NY, USA
pp. 0089

An approach to dynamic power consumption current testing of CMOS ICs (Abstract)

J.A. Segura , Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
M. Roca , Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
D. Mateo , Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
A. Rubio , Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
pp. 0095

Iddt testing of continuous-time filters (Abstract)

J. Arguelles , Dept. de Electron., Cantabria Univ., Santander, Spain
M.J. Lopez , Dept. de Electron., Cantabria Univ., Santander, Spain
J. Blanco , Dept. de Electron., Cantabria Univ., Santander, Spain
M. Martinez , Dept. de Electron., Cantabria Univ., Santander, Spain
S. Bracho , Dept. de Electron., Cantabria Univ., Santander, Spain
pp. 0101
Session 4: Advanced BIST Approaches

On shrinking wide compressors (Abstract)

J. Savir , IBM Corp., Hopewell Junction, NY, USA
pp. 0108

Signature analysis and aliasing for sequential circuits (Abstract)

A.P. Stroele , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 0118

An apparatus for pseudo-deterministic testing (Abstract)

S.K. Mukund , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
T.R.N. Rao , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 0125

Arithmetic built-in self test for high-level synthesis (Abstract)

N. Mukherjee , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
H. Kassab , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
J. Rajski , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
J. Tyszer , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
pp. 0132

Real-time on-board bus testing (Abstract)

J.A. Floyd , Semicond Product Center, Motorola Inc., Austin, TX, USA
M. Perry , Semicond Product Center, Motorola Inc., Austin, TX, USA
pp. 0140
Session 5: Synthesis for Testability

Resynthesis for sequential circuits designed with a specified initial state (Abstract)

H. Yotsuyanagi , Dept. of Appl. Phys., Osaka Univ., Japan
S. Kajihara , Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 0152

A distance reduction approach to design for testability (Abstract)

F.F. Hsu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 0158

An optimized testable architecture for finite state machines (Abstract)

Ting-Yu Kuo , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Chun-Yeh Liu , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
K.K. Saluja , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 0164

Testability metrics for synthesis of self-testable designs and effective test plans (Abstract)

K. Vahidi , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 0170

RT level testability-driven partitioning (Abstract)

Xinli Gu , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
pp. 0176
Session 6: Fault Modeling

The concept of resistance interval: a new parametric model for realistic resistive bridging fault (Abstract)

M. Renovell , Lab. d'Informatique, Robotique et Microelectronique, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Huc , Lab. d'Informatique, Robotique et Microelectronique, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Y. Bertrand , Lab. d'Informatique, Robotique et Microelectronique, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 0184

High level fault modeling of asynchronous circuits (Abstract)

Ding Lu , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
C.Q. Tong , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 0190

Checking experiments to test latches (Abstract)

S.R. Makar , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 0196

Testability of floating gate defects in sequential circuits (Abstract)

V.H. Champac , Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico
J. Figueras , Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico
pp. 0202

Switch-level modeling of transistor-level stuck-at faults (Abstract)

P. Liden , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
P. Dahlgren , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
pp. 0208
Session 7: Fault Simulation I

Simulation of at-speed tests for stuck-at faults (Abstract)

T.J. Chakraborty , AT&T Bell Labs., Princeton, NJ, USA
V.D. Agrawal , AT&T Bell Labs., Princeton, NJ, USA
pp. 0216

VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits (Abstract)

R. Nair , Synopsys Inc., Mountain View, CA, USA
Dong Sam Ha , Synopsys Inc., Mountain View, CA, USA
pp. 0221

Fault coverage analysis of RAM test algorithms (Abstract)

M. Riedel , MACS Lab., McGill Univ., Montreal, Que., Canada
J. Rajski , MACS Lab., McGill Univ., Montreal, Que., Canada
pp. 0227

Reliability evaluation of combinational logic circuits by symbolic simulation (Abstract)

A. Bogliolo , DEIS, Bologna Univ., Italy
M. Damiani , DEIS, Bologna Univ., Italy
P. Olivo , DEIS, Bologna Univ., Italy
B. Ricco , DEIS, Bologna Univ., Italy
pp. 0235
Session 8: Fault Diagnosis

Improving the efficiency of error identification via signature analysis (Abstract)

C.E. Stroud , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
T.R. Damarla , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
pp. 0244

Diagnosis of scan path failures (Abstract)

S. Edirisooriya , Motorola Comput. Group, USA
G. Edirisooriya , Motorola Comput. Group, USA
pp. 0250

Diagnosis of interconnects and FPICs using a structured walking-1 approach (Abstract)

T. Liu , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
J. Salinas , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 0256

Detection and location of faults and defects using digital signal processing (Abstract)

C. Thibeault , Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
pp. 0262
Session 9: Design for Testability

Asynchronous multiple scan chains (Abstract)

S. Narayanan , Sun Microsyst. Inc., Mountain View, CA, USA
M.A. Breuer , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 0270

Partial scan designs without using a separate scan clock (Abstract)

Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 0277

A partial scan methodology for testing self-timed circuits (Abstract)

A. Khoche , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
E. Brunvand , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 0283

On the design of at-speed testable VLSI circuits (Abstract)

M. Soufi , Ecole Polytech. de Montreal, Que., Canada
Y. Savaria , Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Ecole Polytech. de Montreal, Que., Canada
pp. 0290

Scan testing of micropipelines (Abstract)

O.A. Petlin , Dept. of Comput. Sci., Manchester Univ., UK
S.B. Furber , Dept. of Comput. Sci., Manchester Univ., UK
pp. 0296
Session 10: Iddq Testing

Test pattern generation for I/sub DDQ/: increasing test quality (Abstract)

M. Dalpasso , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
P. Olivo , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 0304

Compact test generation for bridging faults under I/sub DDQ/ testing (Abstract)

R.S. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S. Kajihara , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 0310

CURRENT: a test generation system for I/sub DDQ/ testing (Abstract)

U. Mahlstedt , Inst. fur Theor. Elektrotech., Hannover Univ., Germany
J. Alt , Inst. fur Theor. Elektrotech., Hannover Univ., Germany
M. Heinitz , Inst. fur Theor. Elektrotech., Hannover Univ., Germany
pp. 0317

Detecting I/sub DDQ/ defective CMOS circuits by depowering (Abstract)

J. Rius , Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras , Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 0324

Test preparation for high coverage of physical defects in CMOS digital ICs (Abstract)

M.B. Santos , INESC, Lisbon, Portugal
M. Simoes , INESC, Lisbon, Portugal
I. Teixeira , INESC, Lisbon, Portugal
J.P. Teixeira , INESC, Lisbon, Portugal
pp. 0330
Session 11: Automatic Test Pattern Generation

Improving topological ATPG with symbolic techniques (Abstract)

F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
U. Glaser , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
H.T. Vierhaus , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 0338

A scheduling problem in test generation (Abstract)

T. Inoue , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
H. Maeda , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
H. Fujiwara , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
pp. 0344

Detectable perturbations: a paradigm for technology-specific multi-fault test generation (Abstract)

A. Zemva , Ljubljana Univ., Slovenia
F. Brglez , Ljubljana Univ., Slovenia
pp. 0350

Compact test sets for industrial circuits (Abstract)

M.H. Konijnenburg , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
J.T. van der Linden , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 0358

Reducing test application time in scan design schemes (Abstract)

B. Vinnakota , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
N.J. Stessman , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 0367
Session 12: Delay Fault Testing

Generation of high quality tests for functional sensitizable paths (Abstract)

A. Krstic , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 0374

Diagnostic of path and gate delay faults in non-scan sequential circuits (Abstract)

P. Girard , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
B. Rodriguez , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 0380

On the application of local circuit transformations with special emphasis on path delay fault testability (Abstract)

H. Hengster , Dept. of Comput. Sci., Frankfurt Univ., Germany
R. Drechsler , Dept. of Comput. Sci., Frankfurt Univ., Germany
B. Becker , Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 0387

Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming (Abstract)

I.P. Shaik , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 0393

Multifault testability of delay-testable circuits (Abstract)

W. Ke , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
P.R. Menon , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 0400
Session 13: Test Pattern Generation for BIST

Transformed pseudo-random patterns for BIST (Abstract)

N.A. Touba , Dept. of Electr. Eng., Stanford Univ., CA, USA
E.J. McCluskey , Dept. of Electr. Eng., Stanford Univ., CA, USA
pp. 0410

A novel pattern generator for near-perfect fault-coverage (Abstract)

M. Chatterjee , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.K. Pradhan , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 0417

Decompression of test data using variable-length seed LFSRs (Abstract)

N. Zacharia , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
J. Rajski , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
J. Tyszer , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
pp. 0426

Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits (Abstract)

S. Lejmi , Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Ecole Polytech. de Montreal, Que., Canada
B. Ayari , Ecole Polytech. de Montreal, Que., Canada
pp. 0434

Synthesis of locally exhaustive test pattern generators (Abstract)

G. Kemnitz , Inst. fur Tech. Inf., Tech. Univ. Dresden, Germany
pp. 0440
Session 14: Self-Checking Systems I

An approach for system tests design and its application (Abstract)

S.K. Shoukourian , Dept. of Comput. Sci. & Numerical Math., Yerevan State Univ., Armenia
A.G. Kostanian , Dept. of Comput. Sci. & Numerical Math., Yerevan State Univ., Armenia
V.A. Margarian , Dept. of Comput. Sci. & Numerical Math., Yerevan State Univ., Armenia
A.A. Ashour , Dept. of Comput. Sci. & Numerical Math., Yerevan State Univ., Armenia
pp. 0448

Synthesis of combinational circuits with special fault-handling capabilities (Abstract)

A. Bogliolo , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
M. Damiani , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 0454

A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers (Abstract)

S. Brown , AMCC, San Diego, CA, USA
G. Gutierrez , AMCC, San Diego, CA, USA
R. Nelson , AMCC, San Diego, CA, USA
C. VanKrevelen , AMCC, San Diego, CA, USA
pp. 0467

An experimental evaluation of the differential BICS for I/sub DDQ/ testing (Abstract)

W.W. Weber , Dept. of Electr. Eng., Auburn Univ., AL, USA
A.D. Singh , Dept. of Electr. Eng., Auburn Univ., AL, USA
pp. 0472
Best Paper - 1994

Structural constraints for circular self-test paths (Abstract)

J. Carletta , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
C. Papachristou , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
pp. 0486

Author Index (PDF)

pp. 0492
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