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2013 IEEE 31st VLSI Test Symposium (VTS) (1995)
Princeton, New Jersey
Apr. 30, 1995 to May 3, 1995
ISBN: 0-8186-7000-2
pp: 0158
F.F. Hsu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
ABSTRACT
Abstract: The average distance between states is proposed as a new testability measure for finite state machines (FSMs). Also proposed is the concept of center state to reduce distances in FSMs. This test function embedding technique has been shown to improve the testability of sequential circuits with minimal overhead. An overview of several design for testability (DFT) and synthesis for testability (SFT) methods for sequential circuits is also given in this paper. Experimental results have shown that DFT approach is more advantageous than SFT approach to implement our test function. The contribution of this paper is to analyze the trade-offs between several aspects of DFT and SFT techniques.
INDEX TERMS
design for testability; finite state machines; logic testing; sequential circuits; flip-flops; distance reduction approach; design for testability; average distance; finite state machines; center state; test function embedding technique; sequential circuits; synthesis for testability; test function; SFT techniques; DFT techniques; flip-flops
CITATION
F.F. Hsu, J.H. Patel, "A distance reduction approach to design for testability", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 0158, 1995, doi:10.1109/VTEST.1995.512631
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