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2013 IEEE 31st VLSI Test Symposium (VTS) (1995)
Princeton, New Jersey
Apr. 30, 1995 to May 3, 1995
ISBN: 0-8186-7000-2
pp: 0089
V. Dabholkar , State Univ. of New York, Buffalo, NY, USA
S. Chakravarty , State Univ. of New York, Buffalo, NY, USA
J. Najm , State Univ. of New York, Buffalo, NY, USA
J. Patel , State Univ. of New York, Buffalo, NY, USA
ABSTRACT
Abstract: To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in process the circuit needs to be stressed for an extended period of time. This requires computation of cyclic input sequences to stress the circuit. A taxonomy of stress related problems for full scan circuits is presented. It is shown that there are efficient ways to compute the sequences for many variations of monitored burn-in problems. Preliminary experimental results on ISCAS89 benchmark circuits are presented.
INDEX TERMS
integrated circuit reliability; integrated circuit testing; VLSI; CMOS logic circuits; logic testing; boundary scan testing; cyclic stress tests; full scan circuits; fully testable unpackaged dies; MCMs; burn-in process; cyclic input sequences; stress related problems; ISCAS89 benchmark circuits; monitored burn-in problems; VLSI; IC reliability; CMOS
CITATION
V. Dabholkar, S. Chakravarty, J. Najm, J. Patel, "Cyclic stress tests for full scan circuits", 2013 IEEE 31st VLSI Test Symposium (VTS), vol. 00, no. , pp. 0089, 1995, doi:10.1109/VTEST.1995.512622
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