The Community for Technology Leaders
Low-Power Design, IEEE Alessandro Volta Memorial Workshop on (1999)
Como, Italy
Mar. 4, 1999 to Mar. 5, 1999
ISBN: 0-7695-0019-6

Foreword (PDF)

pp. viii
Session A: Keynote Address
Session B: Invited Talks

Are Early Computer Architectures a Source of Ideas for Low-Power? (Abstract)

C. Piguet , CSEM Centre Suisse d'Electronique et de Microtechnique
pp. 4
Session C: Embedded Tutorials

Low-Power VLSI Techniques for Applications in Embedded Computing (Abstract)

William Athas , University of Southern California
pp. 14
Session 1: Low-Power Design Methods and Architectures

Reduced Power Dissipation Through Truncated Multiplication (Abstract)

Michael J. Schulte , Lehigh University
James E. Stine , Lehigh University
John G. Jansen , Lucent Technologies
pp. 61
Session 2: Posters

A CMOS Power-Delay Model for CAD Optimization Tools (Abstract)

M. Delaurenti , Politecnico di Torino
G. Masera , Politecnico di Torino
G. Piccinini , Politecnico di Torino
M. Ruo Roch , Politecnico di Torino
M. Zamboni , Politecnico di Torino
pp. 72

Transformation-Based Peak Power Reduction for Test Sequences (Abstract)

F. Corno , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 78


Martin Margala , University of Alberta
Nelson G. Durdle , University of Alberta
pp. 84

RTL Power Estimation in an Industrial Design Flow (Abstract)

Carlo Guardiani , SGS-Thomson Microelectronics
Massimo Rossello , SGS-Thomson Microelectronics
Roberto Zafalon , SGS-Thomson Microelectronics
Alberto Macii , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Massimo Poncino , Politecnico di Torino
Riccardo Scarsi , Politecnico di Torino
Cristina Silvano , Universita` di Brescia
pp. 91
Session 3: Power Modeling and Estimation I

A New Short Circuit Power Model for Complex CMOS Gates (Abstract)

Qi Wang , Cadence Design Systems
Sarma B.K. Vrudhula , The University of Arizona
pp. 98

A Comparison of Stream Synthesis Methods for Fast Power Simulation (Abstract)

Alberto Macii , Politecnico di Torino
Riccardo Scarsi , Politecnico di Torino
pp. 107

Maximum Leakage Power Estimation for CMOS Circuits (Abstract)

S. Bobba , University of Illinois at Urbana-Champaign
I.N. Hajj , University of Illinois at Urbana-Champaign
pp. 116
Session 4: Low-Power Circuits

Will VLSI Digital Circuits Exist in GaAs? (Abstract)

R. Kanan , Swiss Federal Institute of Technology
M. Declercq , Swiss Federal Institute of Technology
pp. 126

Pipelined DSP Design with a True Single-Phase Energy-Recovering Logic Style (Abstract)

Suhwan Kim , Advanced Computer Architecture Laboratory
Marios C. Papaefthymiou , Advanced Computer Architecture Laboratory
pp. 135

Mismatch-Shaped Pseudo-Passive Two-Capacitor DAC (Abstract)

Jesper Steensgaard , The Technical University of Denmark
Un-Ku Moon , Oregon State University
Gabor Temes , Oregon State University
pp. 144
Session 5: Power Modeling and Estimation II

Analytical Model for High Level Power Modeling of Combinational and Sequential Circuits (Abstract)

Subodh Gupta , University of Illinois at Urbana-Champaign
Farid N. Najm , University of Illinois at Urbana-Champaign
pp. 164

A Data Dependent Approach to Instruction Level Power Estimation (Abstract)

Davide Sarta , STMicroelectronis
Dario Trifone , STMicroelectronis
Giuseppe Ascia , University of Catania
pp. 182

Efficient Power Estimation Techniques for HW/SW Systems (Abstract)

Marcello Lajolo , Politecnico di Torino
Luciano Lavagno , Politecnico di Torino
Sujit Dey , University of California at San Diego
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 191

Author Index (PDF)

pp. 202
89 ms
(Ver 3.3 (11022016))