2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) (2018)
Jan. 6, 2018 to Jan. 10, 2018
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2018.37
Embedded systems that are employed in safety-critical applications require highest reliability. External watchdog timers are used in such systems to automatically handle and recover from operation time related failures. Most of the available external watchdog timers use additional circuitry to adjust their timeout periods and provide only limited features in terms of their functionality. This paper describes the architecture and design of an improved configurable watchdog timer that can be employed in safety-critical applications. Several fault detection mechanisms are built into the watchdog, which adds to its robustness. The functionality and operations are rather general and it can be used to monitor the operations of any processor based real-time system. This paper also discusses the implementation of the proposed watchdog timer in a Field Programmable Gate Array (FPGA). This allows the design to be easily adaptable to different applications, while reducing the overall system cost. The effectiveness of the proposed watchdog timer to detect and respond to faults is first studied by analysing the simulation results. The design is validated in a real-time hardware by injecting faults through the software while the processor is executing, and conclusions are drawn.
embedded systems, fault diagnosis, field programmable gate arrays, real-time systems, timing circuits
R. K. Unni, V. P. and Y. Dilip, "FPGA Implementation of an Improved Watchdog Timer for Safety-Critical Applications," 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, India, 2018, pp. 55-60.