VLSI Design, International Conference on (2011)
Madras, Chennai India
Jan. 2, 2011 to Jan. 7, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2011.74
A reconfigurable processor tailored for accelerating Phylogenetic Inference is proposed. In this paper, a programmable and scalable architectural platform instantiates an array of coarse grained light weight processing elements and allows arbitrary partitioning and scheduling schemes and capable of solving complete Maximum Likelihood algorithm and deal with arbitrarily large sequences. The key difference of the proposed CGRA based solution compared to FPGA and GPU based solutions is a much better match of the architecture and algorithm for the core computational need as well as the system level architectural need. For the same degree of parallelism, we provide a 2.27X speed-up improvements compared to FPGA with the same amount of core logic, and an 81.87X speed-up improvements compared to GPU with the same silicon area respectively.
Phylogenetic Inference, Maximum Likelihood Algorithm, Phylogenetic Likelihood Function, Coarse Grain Reconfigurable Architecture, VLSI
Kolin Paul, Ahmed Hemani, Pei Liu, "A Reconfigurable Processor for Phylogenetic Inference", VLSI Design, International Conference on, vol. 00, no. , pp. 226-231, 2011, doi:10.1109/VLSID.2011.74