2009 22nd International Conference on VLSI Design (2009)
Jan. 5, 2009 to Jan. 9, 2009
Manufacturing and operation-induced variations have emerged as a critical challenge in designing integrated circuits (ICs) under the nanometer technology regime. Most work on addressing variations has focused on device, circuit, and logic-level solutions. As the magnitude of parameter variations increases with technology scaling, these techniques are not sufficient to address the negative impact that variations have on IC performance, power, yield, and design time. Therefore, in recent years, the research community has shown great interest in techniques to address variations starting from the other end of the design process, i.e., at the system level. In this paper, we provide an overview of various techniques that we have developed for coping with variations through system-level design. The presented techniques include a paradigm for designing variation-tolerant systems through critical path isolation for timing adaptiveness, application-specific techniques to achieve variation-tolerance by trading off quality of the result, variation-aware system-level power analysis, and system-level power management under variations. These techniques demonstrate that addressing variations during system-level design can greatly mitigate the effects of variations, enabling the design of integrated circuits in scaled technologies.
Integrated Circuits, Nanoscale, System-on-chip, variations, system-level design
K. Roy, S. Dey, S. Chandra, N. Banerjee, A. Raghunathan and S. Ghosh, "Coping with Variations through System-Level Design," 2009 22nd International Conference on VLSI Design(VLSID), New Delhi, 2009, pp. 581-586.