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2008 21st International Conference on VLSI Design (2008)
Hyderabad
Jan. 4, 2008 to Jan. 8, 2008
ISSN: 1063-9667
ISBN: 0-7695-3083-4
pp: 17-18
ABSTRACT
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power specifications. Frequency specifications of high-end realizations are often nearly 2x-3x over vanilla flows. Power optimization techniques used in high-end processor designs have also been reported to have the potential to produce 3x-10x improvements in power over standard flows. This tutorial reviews high-end processor design challenges, techniques and presents state-of-the-art flows for implementing embedded processors. These techniques include processor and architecture selection, verification, selection of technology node/process, selection of macros, selection and optimization of standard cell libraries, design/architecture and power planning, advanced timing and power optimization, design closure, design integration, variability-tolerance, and design-formanufacturability. The tutorial arms the audience with the best techniques, tools and methodologies to select and achieve the best Silicon for state-of-the-art embedded processors.
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CITATION
Rahoul Varma, Vamsi Boppana, S. Balajee, "Implementing the Best Processor Cores", 2008 21st International Conference on VLSI Design, vol. 00, no. , pp. 17-18, 2008, doi:10.1109/VLSI.2008.137
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