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VLSI Design, International Conference on (2005)
Kolkata, India
Jan. 3, 2005 to Jan. 7, 2005
ISSN: 1063-9667
ISBN: 0-7695-2264-5
pp: 799-803
N. Gupta , University of Manchester
D. A. Edwards , University of Manchester
ABSTRACT
<p>Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable state until necessary wire transitions trigger an event to occur. This avoids synchronizing events using a global clock tree, which can consume a large amount of energy. The need for low power and high performance circuits leads to investigation of various asynchronous design styles.</p> <p>The work presented here provides an overview and novel implementation of synthesizing asynchronous circuits using an early data validity protocol. Conventional asynchronous tools synthesize circuits using a broad data validity protocol, which leads to simple circuits, but non-overlapped sequencing of consecutive operations. The early protocol requires data to be valid for a shorter period, allowing consecutive operations to overlap phases. The resulting circuits have a potential increase in performance by allowing greater concurrency and earlier execution of events.</p>
INDEX TERMS
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CITATION
N. Gupta, D. A. Edwards, "Synthesis of Asynchronous Circuits Using Early Data Validity", VLSI Design, International Conference on, vol. 00, no. , pp. 799-803, 2005, doi:10.1109/ICVD.2005.156
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