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VLSI Design, International Conference on (2002)
Bangalore, India
Jan. 7, 2002 to Jan. 11, 2002
ISBN: 0-7695-1441-3
pp: 51
Kewal K. Saluja , University of Wisconsin-Madison
Lei He , University of Wisconsin-Madison
Fei Li , University of Wisconsin-Madison
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-gated circuit must be brought to a valid state from the power-off state, when all nodes in the circuit are at logic zero state, before useful computation can begin. Thus, estimation of the maximum current in a power gated circuit must determine the maximum of all possible power-up and normal switching current. In this paper, we propose a cluster-based ATPG algorithm to estimate the maximum power-up current for combinational circuits. Our method achieves substantial improvement over simulation-based methods and also over the previously proposed ATPG-based methods. Further, we also formulate the sequential circuit maximum current problem as a combinational ATPG problem, and solve it using the cluster-based estimation algorithm. Experimental results show that the maximum power-up current for sequential circuits can be up to 73% larger than the maximum normal switching current.
current estimation, leakage reduction, ATPG algorithm
Kewal K. Saluja, Lei He, Fei Li, "Estimation of Maximum Power-up Current", VLSI Design, International Conference on, vol. 00, no. , pp. 51, 2002, doi:10.1109/ASPDAC.2002.994884
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