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VLSI Design, International Conference on (2001)
Bangalore, India
Jan. 3, 2001 to Jan. 7, 2001
ISSN: 1063-9667
ISBN: 0-7695-0831-6
pp: 333
Sreejit Chakravarty , Intel Corporation
Sujit T. Zachariah , Intel Corporation
ABSTRACT
Defects that short two or more nodes are known as multi-node bridges. Multinode bridge analysis can be used to extract a list of either only two-node bridges or multi-node bridges. We discuss why multi-node bridge analysis is also required even if only two-node bridges are targeted. We propose a novel, scalable and accurate algorithm for multi-node bridge analysis of large layouts. CARAFE can perform multi-node analysis only on small layouts. Comparison results show that for small layouts our algorithm is considerably faster than CARAFE. For larger layouts experimental results are provided to illustrate the performance and capacity of our algorithm.
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CITATION
Sreejit Chakravarty, Sujit T. Zachariah, "A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits", VLSI Design, International Conference on, vol. 00, no. , pp. 333, 2001, doi:10.1109/ICVD.2001.902681
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