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VLSI Design, International Conference on (2000)
Calcutta, India
Jan. 4, 2000 to Jan. 7, 2000
ISSN: 1063-9667
ISBN: 0-7695-0487-6
pp: 556
Vamsi Boppana , Fujitsu Laboratories of America Inc.
Kolin Paul , Bengal Engineering College (D.U)
Cliff Yang , Fujitsu-WWSLT Ltd.
Biplab K. Sikdar , Bengal Engineering College (D.U)
Gosta Pada Biswas , Bengal Engineering College (D.U)
P. Pal Chaudhuri , Bengal Engineering College (D.U)
Sobhan Mukherjee , Fujitsu-WWSLT Ltd.
This paper sets a new direction for test solution of VLSI circuits. The solution is based on the theory of extension field-- that is, extension of finite field commonly referred to as Galois Field GF. The GF(2) with the set (0, 1) traditionally employed in the digital domain has been extended in the present work to GF(2**p) with elements from the set (0, 1, 2,..., 2**(p-1)). The conventional on-chip LFSR/Cellular Automata (CA) based test pattern generators built around GF(2) elements have been replaced with the cellular structure of GF(2**p) CA. The inter-cell connections and the value of p of a regular, modular and cascadable structure of GF(2**p) CA can be tuned to maximize the fault coverage in a CUT (Circuit Under Test). Availability of RTL/functional description of the CUT leads to a better tuning. The fault coverage figures obtained with GF(2**p) CA based test pattern generator on the benchmark circuits and a few commercial circuits can be found to be significantly better than the best results reported so far with LFSR, GLFSR or GF(2) CA. The small set of uncovered faults can be handled with the introduction of a limited number of observation and test points. Area overhead for CATPG can be significantly reduced through the scheme of folding introduced in this paper.
Finite field, Extension field, BIST structure, DFT, Cellular Automata (CA), LFSR, Fault coverage, VLSI design and RTL
Vamsi Boppana, Kolin Paul, Cliff Yang, Biplab K. Sikdar, Gosta Pada Biswas, P. Pal Chaudhuri, Sobhan Mukherjee, "Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator", VLSI Design, International Conference on, vol. 00, no. , pp. 556, 2000, doi:10.1109/ICVD.2000.812666
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