Jan. 4, 1998 to Jan. 7, 1998
Ananta K. Majhi , Mentor Graphics Ltd.
Vishwani D. Agrawal , Bell Labs
Failures that cause logic circuits to malfunction at the desired clock rate and thus violate timing specifications are currently receiving much attention. Such failures are modeled as delay faults. They facilitate delay testing. The use of delay fault models in VLSI test generation is very likely to gain industry acceptance in the near future. In this paper, we review delay fault models, discuss their classifications and examine fault coverage metrics that have been proposed in the recent literature. A comparison between delay fault models, namely, gate delay, transition, path delay, line delay and segment delay faults, shows their benefits and limitations. Various classifications of path delay fault models, that have received the most attention in recent years, are reviewed. We believe an understanding of delay fault models is essential in today's VLSI design and test environment.
Delay test, delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model.
Ananta K. Majhi, Vishwani D. Agrawal, "Tutorial: Delay Fault Models and Coverage", VLSID, 1998, VLSI Design, International Conference on, VLSI Design, International Conference on 1998, pp. 364, doi:10.1109/ICVD.1998.646634