The Community for Technology Leaders
VHDL International User's Forum (1997)
Arlington, VA
Oct. 19, 1997 to Oct. 22, 1997
ISBN: 0-8186-8180-2
TABLE OF CONTENTS
Session 1: Verification

Implementing A Complete Test Tool Set In VHDL (Abstract)

Z. Navabi , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
A. Peymandoust , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 2

Using WAVES For Verification Of Synthesized Sub-Components In A Deeply Hierarchical Design (Abstract)

L. Concha , Res. & Dev. Center, Wright-Patterson AFB, OH, USA
P. Jarusiewic , Res. & Dev. Center, Wright-Patterson AFB, OH, USA
B. Read , Res. & Dev. Center, Wright-Patterson AFB, OH, USA
K. Olson , Res. & Dev. Center, Wright-Patterson AFB, OH, USA
B. Kadrovach , Res. & Dev. Center, Wright-Patterson AFB, OH, USA
R. Bishop , Res. & Dev. Center, Wright-Patterson AFB, OH, USA
pp. 11

Functional Fault Simulation of VHDL Gate Level Models (Abstract)

S.A. Aftabjahani , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Z. Navabi , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
pp. 18
Session 2: Performance Modeling

Mixed-Level Modeling In VHDL Using The Watch-And-React Interface (Abstract)

R.H. Klenke , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
W.W. Dungan , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.H. Aylor , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 25

Rapid-Prototyping Of High-Performance RISC Cores with VHDL (Abstract)

P.P. Carballo , CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
G. Marrero , CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
A. Nunez , CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
T. Bautista , CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
pp. 43
Session 3: OO-VHDL

OOVHDL: Object Oriented VHDL (Abstract)

B. Djafri , LaMI Lab., Evry Univ., France
J. Benzakki , LaMI Lab., Evry Univ., France
pp. 54

SUAVE: Painless Extension For An Object-Oriented VHDL (Abstract)

D.E. Martin , Dept. of Comput. Sci., Adelaide Univ., SA, Australia
P.J. Ashenden , Dept. of Comput. Sci., Adelaide Univ., SA, Australia
P.A. Wilsey , Dept. of Comput. Sci., Adelaide Univ., SA, Australia
pp. 60

A Requirements Analysis of Proposed Object Oriented VHDL Abstractions (Abstract)

Michael T. Mills , LtCol USAF Reserve, WL/AAS, Wright-Patterson AFB OH
pp. 68
Session 4: Synthesis

Fast Prototyping of an ASIC for ATM Application Using a Synthesizable VHDL Flexible Library (Abstract)

Serafino Claretto , CSELT- Centro Studi e Laboratori Telecomunicazioni
Maura Turolla. , CSELT- Centro Studi e Laboratori Telecomunicazioni
Enrica Filippi , CSELT- Centro Studi e Laboratori Telecomunicazioni
Maurizio Paolini , CSELT- Centro Studi e Laboratori Telecomunicazioni
Achille Montanaro , CSELT- Centro Studi e Laboratori Telecomunicazioni
pp. 88
Session 5: System Level Modeling

Extending VHDL to the Systems Level (Abstract)

Perry Alexander , The University of Cincinnati
Phillip Baraona , The University of Cincinnati
pp. 96

Semantics Based Co-Specifications To Design DSP Systems (Abstract)

Xavier Warzee , Thomson-CSF Optronique, France
P. Kajfasz , Thomson-CSF Optronique, France
pp. 105

Proposing Graphic Extensions to VHDL (Abstract)

T. Hadlich , Inst. of Autom., Magdeburg Univ., Germany
pp. 109
Session 6: Model Generation and Metrics

RTL Based Scan BIST (Abstract)

Subrata Roy , Lucent Technologies, Bell Laboratories
pp. 117

Supporting Hardware Trade Analysis And Cost Estimation Using Design Complexity (Abstract)

P.W. Salchak , Symvionics Inc., Beavercreek, OH, USA
P. Chawla , Symvionics Inc., Beavercreek, OH, USA
pp. 126
Session 7: FPGAs

SCUBA: An HDL Data-Path/Memory Module Generator for FPGAs (Abstract)

Shinichiro Haruyama , Bell Laboratories, Lucent Technologies Inc.
Jiang Niu , Bell Laboratories, Lucent Technologies Inc.
Sidhartha Mohanty , Bell Laboratories, Lucent Technologies Inc.
Kapilan Maheswaran , Bell Laboratories, Lucent Technologies Inc.
pp. 135

Use of VHDL within a System Level Design Flow (Abstract)

T. Hadlich , Inst. of Autom., Magdeburg Univ., Germany
pp. 150
Session 8: Legacy++

Extraction of Token Based VHDL Models From Old ASIC Net Lists (Abstract)

D. Soderberg , Electron. Lab., Defence Mater. Adm., Linkoping, Sweden
pp. 157

VHDL Design Environment for Legacy Electronics (VDELE) III (Abstract)

Randall Bohannan , Sanders, A Lockheed-Martin Company
Luis Concha , WL/AASE, WPAFB, Ohio
pp. 162

Reuse Through Genericity in SUAVE (Abstract)

P.J. Ashenden , Dept. of Comput. Sci., Adelaide Univ., SA, Australia
P.A. Wilsey , Dept. of Comput. Sci., Adelaide Univ., SA, Australia
D.E. Martin , Dept. of Comput. Sci., Adelaide Univ., SA, Australia
pp. 170
Session R1: RASSP Model Library

VHDL Modeling And Tutoring Efforts by Mississippi State University (Abstract)

R.B. Reese , Mississippi State Univ., MS, USA
D.T. Brown , Mississippi State Univ., MS, USA
pp. 179

VHDL Models Supporting A System-Level Design Process: A RASSP Approach (Abstract)

J.A. DeBardelaben , Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA
V.K. Madisetti , Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA
A.J. Gadient , Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 183
Session R2: Performance Modeling

Improvements to ADEPT-a VHDL Based Integrated Design Environment For Performance And Dependability Analysis (Abstract)

M. Meyassed , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
R.H. Klenke , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.H. Aylor , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
B.W. Johnson , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
W.W. Dungan , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
R. Rao , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
C.Y. Choi , Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 190
Session 9: Test Benches and Reliability Analysis

Component modeling for reliability analysis by simulation (Abstract)

Z. Navabi , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
B. Alizadeh , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
pp. 225
Session R3: Potpourri

A model-year architecture approach to hardware reuse in digital signal processor system design (Abstract)

J. Wedgwood , Lockheed Martin Adv. Technol. Labs., Camden, NJ, USA
G. Buchanan , Lockheed Martin Adv. Technol. Labs., Camden, NJ, USA
pp. 231
Session 10: Mixed Nuts

IEEE VHDL 1076.1: mixed-signal behavioral modeling and verification in view of automotive applications (Abstract)

J. Papanuskas , Autom. Equipment Div., Robert Bosch GmbH, Ruetlingen, Germany
pp. 252

A hybrid event-simulation/cycle-simulation environment for VHDL-based designs (Abstract)

D.E. Wood , IBM Corp., Rochester, MN, USA
M.C. Cogswell , IBM Corp., Rochester, MN, USA
pp. 258

On Comparing Different Modeling Styles (Abstract)

Joerg Boettger , Siemens AG
Wolfgang Ecker , Siemens AG
pp. 264

A new methodology and generic model library for the rapid prototyping of real-time image processing systems (Abstract)

M. Winchester , Sch. of Design, Eng. & Comput., Bournemouth Univ., Poole, UK
D.J. Gibson , Sch. of Design, Eng. & Comput., Bournemouth Univ., Poole, UK
D. Ait-Boudaoud , Sch. of Design, Eng. & Comput., Bournemouth Univ., Poole, UK
M.K. Teal , Sch. of Design, Eng. & Comput., Bournemouth Univ., Poole, UK
pp. 268
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