The Community for Technology Leaders
2015 19th International Symposium on VLSI Design and Test (VDAT) (2015)
Ahmedabad, India
June 26, 2015 to June 29, 2015
ISBN: 978-1-4799-1742-6
TABLE OF CONTENTS

Design and development of cantilever-type MEMS based piezoelectric energy harvester (Abstract)

Shanky Saxena , Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jaipur 302017
Ritu Sharma , Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jaipur 302017
B.D. Pant , MEMS and Microsensors Group, Central Electronics Engineering Research Institute, Pilani 333031
pp. 1-4

Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology (Abstract)

Rakesh Trivedi , ISRO-RESPOND Programme, Nirma University, Ahmedabad
N. M. Devashrayee , EC Department, Nirma University, Ahmedabad
Usha S Mehta , EC Department, Nirma University, Ahmedabad
N. M. Desai , Space Application Center - Indian Space Research Organization (SAC-ISRO), Ahmedabad
Himanshu Patel , Space Application Center - Indian Space Research Organization (SAC-ISRO), Ahmedabad
pp. 1-2

Thermal aware AND-OR-XOR network synthesis (Abstract)

Priyanka Choudhury , Electronics and Communication Engineering Department, National Institute of Technology Agartala, Agartala, India
Debanjali Nath , Electronics and Communication Engineering Department, National Institute of Technology Agartala, Agartala, India
Vivek Rai , Electronics and Communication Engineering Department, National Institute of Technology Agartala, Agartala, India
Sambhu Nath Pradhan , Electronics and Communication Engineering Department, National Institute of Technology Agartala, Agartala, India
pp. 1-6

RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks (Abstract)

Krishnendu Guha , A. K. Choudhury School of I.T., University of Calcutta, Kolkata, India
Debasri Saha , A. K. Choudhury School of I.T., University of Calcutta, Kolkata, India
Amlan Chakrabarti , A. K. Choudhury School of I.T.,. University of Calcutta, Kolkata, India
pp. 1-6

Improved supply regulation and temperature compensated current reference circuit with low process variations (Abstract)

Suraj Gupta , School of VLSI Technology, IIEST, Shibpur, Howrah, India
Sabir Ali Mondal , School of VLSI Technology, IIEST, Shibpur, Howrah, India
Hafizur Rahaman , School of VLSI Technology, IIEST, Shibpur, Howrah, India
pp. 1-6

CORDIC on a configurable serial architecture for biomedical signal processing applications (Abstract)

Nupur Jain , VLSI and Embedded Systems Research Group, Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, 382007 Gujarat
Biswajit Mishra , VLSI and Embedded Systems Research Group, Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, 382007 Gujarat
pp. 1-6

High-performance multiplierless DCT architecture for HEVC (Abstract)

A. D. Darji , Department of Electronics Engineering, S. V. National Institute of Technology, Surat, Gujarat - 395 007
Raviraj P. Makwana , Department of Electronics Engineering, S. V. National Institute of Technology, Surat, Gujarat - 395 007
pp. 1-5

Case study: Re-visiting SoC verification challenges and best practices (Abstract)

Prokash Ghosh , Digital Networking Group, Freescale Semiconductor, Sec-16A, Noida, India
Sandip Ghosh , Digital Networking Group, Freescale Semiconductor, Sec-16A, Noida, India
Pritpal Singh , Digital Networking Group, Freescale Semiconductor, Sec-16A, Noida, India
Saurabh Mishra , Digital Networking Group, Freescale Semiconductor, Sec-16A, Noida, India
pp. 1-9

Area optimized CMOS layouts of a 50 Gb/s low power 4:1 multiplexer (Abstract)

Vibhor Pareek , Electronics and Communication Engineering, The LNMIIT, Jaipur, India
Gaurvi Goyal , Electronics and Communication Engineering, The LNMIIT, Jaipur, India
pp. 1-6

Bipolar voltage level shifter (Abstract)

Hari Shanker Gupta , Sensor Electronics Group, Space Application Centre, ISRO, Ahmedabad, India
Shweta Kirkire , Sensor Electronics Group, Space Application Centre, ISRO, Ahmedabad, India
Sunil Bhati , Sensor Electronics Group, Space Application Centre, ISRO, Ahmedabad, India
Ravi Shankar Chaurasia , Sensor Electronics Group, Space Application Centre, ISRO, Ahmedabad, India
Sanjeev Mehta , Sensor Electronics Group, Space Application Centre, ISRO, Ahmedabad, India
Arup Roy Choudhary , Sensor Electronics Group, Space Application Centre, ISRO, Ahmedabad, India
Dipen Patel , Department of Electronics and Communication Engineering, Gujarat Technological University, Ahmedabad (India)
Jaymin Vaghela , Department of Electronics and Communication Engineering, Gujarat Technological University, Ahmedabad (India)
pp. 1-5

On-chip CMOS temperature sensor with current calibrated accuracy of −1.1°C to +1.4°C (3σ) from −20°C to 150°C (Abstract)

Mudasir Bashir , Department of ECE, NIT, Warangal, India
Sreehari Rao Patri , Department of ECE, NIT, Warangal, India
K S R Krishnaprasad , Department of ECE, NIT, Warangal, India
pp. 1-5

High speed self biased current sense amplifier for low power CMOS SRAM's (Abstract)

Mudasir Bashir , Department of ECE, NIT, Warangal, India
Sreehari Rao Patri , Department of ECE, NIT, Warangal, India
K S R Krishnaprasad , Department of ECE, NIT, Warangal, India
pp. 1-5

σLBDR: Congestion-aware logic based distributed routing for 2D NoC (Abstract)

Niyati Gupta , Malaviya National Institute of Technology, Jaipur, India
Manoj Kumar , Malaviya National Institute of Technology, Jaipur, India
Vijay Laxmi , Malaviya National Institute of Technology, Jaipur, India
Manoj Singh Gaur , Malaviya National Institute of Technology, Jaipur, India
Mark Zwolinski , University of Southampton, Southampton, United Kingdom
pp. 1-6

Defect characterization and testing of QCA devices and circuits: A survey (Abstract)

Vaishali Dhare , Institute of Technology, Nirma University, Ahmedabad
Usha Mehta , Institute of Technology, Nirma University, Ahmedabad
pp. 1-2

A novel dual multiplier floating point multiply accumulate architecture (Abstract)

Rohit Kumar , ABV-Indian Institute of Information Technology and Management, Morena Link Road, Gwalior, Madhya Pradesh, India, 474015
Manisha Pattanaik , ABV-Indian Institute of Information Technology and Management, Morena Link Road, Gwalior, Madhya Pradesh, India, 474015
pp. 1-2

Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies (Abstract)

Arvind Kumar Sharma , Indian Institute of Technology Roorkee, Roorkee, India
Neeraj Mishra , Indian Institute of Technology Roorkee, Roorkee, India
Naushad Alam , Aligarh Muslim University, Aligarh, India
Sudeb Dasgupta , Indian Institute of Technology Roorkee, Roorkee, India
Anand Bulusu , Indian Institute of Technology Roorkee, Roorkee, India
pp. 1-6

A framework for thermal aware reliability estimation in 2D NoC (Abstract)

Ashish Sharma , Malaviya National Institute of Technology, Jaipur, India
Prachi Upadhyay , Poornima College of Engineering, Jaipur, India
Ruby Ansar , Poornima College of Engineering, Jaipur, India
Vijay Laxmi , Malaviya National Institute of Technology, Jaipur, India
Lava Bhargava , Malaviya National Institute of Technology, Jaipur, India
Manoj Singh Gaur , Malaviya National Institute of Technology, Jaipur, India
Mark Zwolinski , University of Southampton, Southampton, United Kingdom
pp. 1-6

An improved AES Hardware Trojan benchmark to validate Trojan detection schemes in an ASIC design flow (Abstract)

K Sudeendra Kumar , National Institute of Technology, Rourkela, India
Rakesh Chanamala , National Institute of Technology, Rourkela, India
Sauvagya Ranjan Sahoo , National Institute of Technology, Rourkela, India
K. K. Mahapatra , National Institute of Technology, Rourkela, India
pp. 1-6

MAC based FIR filter: A novel approach for low-power real-time de-noising of ECG signals (Abstract)

Ramandeep Kaur , Department of Electronics and Communication Engineering, IIIT Delhi, India
Rahul Malhotra , Department of Electronics and Communication Engineering, IIIT Delhi, India
Sujay Deb , Department of Electronics and Communication Engineering, IIIT Delhi, India
pp. 1-5

A novel approach to reusable time-economized STIL based pattern development (Abstract)

Rahul Malhotra , IIIT Delhi
Sujay Deb , IIIT Delhi
Fabio Carlucci , ST Microelectronics, Greater Noida, Uttar Pradesh
pp. 1-5

C2-DLM: Cache coherence aware dual link mesh for on-chip interconnect (Abstract)

Sonal Yadav , MNIT, Jaipur, India
V. Laxmi , MNIT, Jaipur, India
M. S. Gaur , MNIT, Jaipur, India
Megha Bhargava , CCT, University of Rajasthan, Jaipur, India
pp. 1-2

A 4 bit medium speed flash ADC using inverter based comparator in 0.18μm CMOS (Abstract)

D. Malathi , Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India
R. Greeshma , Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India
R. Sanjay , Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India
B. Venkataramani , Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirapalli, India
pp. 1-5

An inductorless receiver front-end for multiband wireless applications (Abstract)

Priyanka Sharma , Dept. of Electronics Engineering, RCOEM, Nagpur, India
Sunil Pandey , Dept. of Electronics Engineering, RCOEM, Nagpur, India
Pravin A. Dwaramwar , Dept. of Electronics Engineering, RCOEM, Nagpur, India
pp. 1-5

A novel adiabatic SRAM cell implementation using split level charge recovery logic (Abstract)

S Dinesh Kumar , Dept. of EDM, IIITD&M Kancheepuram, Chennai - 600 127
S K Noor Mahammad , Dept. of CSE, IIITD&M Kancheepuram, Chennai - 600 127
pp. 1-2

Realistic dynamic timing verification for complex mixed signal hard macro's using UVM (Abstract)

Kunal Parihar , ST Microelectronics, New Delhi, India
M Venkatesh , NIT Warangal, Telangana, India
Ravikumar Patel , ST Microelectronics, New Delhi, India
pp. 1-2

Implementation of high speed radix-10 parallel multiplier using Verilog (Abstract)

Sonam Negi , Dept. of ECE, Graphic Era University, Dehradun, India
Pitchaiah Madduri , Dept. of ECE Graphic Era University, Dehradun, India
pp. 1-5

Implementation of high speed radix-10 parallel multiplier using Verilog (Abstract)

Sonam Negi , Dept. of ECE, Graphic Era University, Dehradun, India
Pitchaiah Madduri , Dept. of ECE Graphic Era University, Dehradun, India
pp. 1-5

Timing model for two stage buffer and its application in ECSM characterization (Abstract)

Yogesh Chaurasiya , Indian Institute of Technology Roorkee, India
Surabhi Bhargava , Indian Institute of Technology Guwahati, India
Arvind Sharma , Indian Institute of Technology Roorkee, India
Baljit Kaur , Jaypee Institute of Information Technology Noida, India
Bulusu Anand , Indian Institute of Technology Roorkee, India
pp. 1-6

Performance optimization of real time control systems using variable time period (Abstract)

Jaishree Mayank , Department of Computer Science & Engineering, Indian Institute of Technology Patna, Patna, India 800013
Arijit Mondal , Department of Computer Science & Engineering, Indian Institute of Technology Patna, Patna, India 800013
pp. 1-6

Intuitive design of PTAT and CTAT circuits for MOSFET based temperature sensor using Inversion Coefficient based approach (Abstract)

Shikhar Tewari , Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, India
Kirmender Singh , Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, India
pp. 1-6

Power aware cache miss reduction by energy efficient victim retention (Abstract)

Shounak Chakraborty , Department of Computer Science and Engineering, IIT Guwahati, Assam, India-781039
Shirshendu Das , Department of Computer Science and Engineering, IIT Guwahati, Assam, India-781039
Hemangee K. Kapoor , Department of Computer Science and Engineering, IIT Guwahati, Assam, India-781039
pp. 1-6

An efficient searching mechanism for dynamic NUCA in chip multiprocessors (Abstract)

Kartheek Vanapalli , Dept. of Computer Science and Engineerging Indian Institute of Technology Guwahati, India
Hemangee K. Kapoor , Dept. of Computer Science and Engineerging Indian Institute of Technology Guwahati, India
Shirshendu Das , Dept. of Computer Science and Engineerging Indian Institute of Technology Guwahati, India
pp. 1-5

Simulation and characterization of dual-gate SOI MOSFET, on-chip fabricated with ISFET (Abstract)

J Yadav , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
S Sinha , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
A Sharma , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
R Chaudhary , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
R Mukhiya , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
R Sharma , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
V K Khanna , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
pp. 1-5

Modeling and synthesis of molecular memory (Abstract)

Renu Kumawat , Department of Electronics & Communication Engg., School of Electrical, Electronics & Communication, Manipal University Jaipur
Vineet Sahula , Department of Electronics & Communication Engg., Malaviya National Institute of Technology, Jaipur
Manoj Singh Gaur , Department of Computer Science & Engg., Malaviya National Institute of Technology, Jaipur
pp. 1-2

An offset-tolerant self-correcting sense amplifier for robust high speed SRAM (Abstract)

Praneet Bhatia , BITS Pilani K. K. Birla Goa Campus
B. S. Reniwal , Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering, Indian Institute of Technology Indore, India
S. K. Vishvakarma , Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering, Indian Institute of Technology Indore, India
pp. 1-6

Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si3N4 ISFET (Abstract)

R Chaudhary , CSIR- Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
A Sharma , CSIR- Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
S Sinha , CSIR- Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
J Yadav , CSIR- Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
R Sharma , CSIR- Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
R Mukhiya , CSIR- Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
V K Khanna , CSIR- Central Electronics Engineering Research Institute (CEERI), Pilani-333031 (Raj.) India
pp. 1-4

An integrable trench LDMOS transistor on SOI for RF power amplifiers in PICs (Abstract)

Mayank Punetha , Department of Electronics and Communication Engineering, G. B. Pant Engineering College, Pauri Garhwal, Uttarakhand-246194, India
Yashvir Singh , Department of Electronics and Communication Engineering, G. B. Pant Engineering College, Pauri Garhwal, Uttarakhand-246194, India
pp. 1-4

An efficient approach for estimating the impact of SSO noise on LPDDR2 timing budget (Abstract)

Yagya D. Mishra , Department of Electronics and Comm. Engineering, IIIT Delhi, New Delhi, India
Mohammad S. Hashmi , Department of Electronics and Comm. Engineering, IIIT Delhi, New Delhi, India
Akhilesh C. Mishra , STMicroelectronics Pvt. Ltd., Greater Noida, India
pp. 1-6

A cost-optimal algorithm for guard zone computation including detection and exclusion of overlapping (Abstract)

Ranjan Mehera , Department of Computer Science and Engineering, University of Calcutta A. P. C. Roy Siksha Prangan, JD-2, Sector - III, Saltlake City, Kolkata - 700 098, West Bengal, India
Arpan Chakraborty , Department of Computer Science and Engineering, University of Calcutta A. P. C. Roy Siksha Prangan, JD-2, Sector - III, Saltlake City, Kolkata - 700 098, West Bengal, India
Piyali Datta , Department of Computer Science and Engineering, University of Calcutta A. P. C. Roy Siksha Prangan, JD-2, Sector - III, Saltlake City, Kolkata - 700 098, West Bengal, India
Rajat Kumar Pal , Department of Computer Science and Engineering, University of Calcutta A. P. C. Roy Siksha Prangan, JD-2, Sector - III, Saltlake City, Kolkata - 700 098, West Bengal, India
pp. 1-6

Real time multisensor Laplacian fusion on FPGA (Abstract)

Kshitij Agrawal , Centre for VLSI and Embedded Systems Technology, IIIT-Hyderabad
Shubhajit Roy Chowdhury , Centre for VLSI and Embedded Systems Technology, IIIT-Hyderabad
pp. 1-4

Partitioning-based test time reduction for core-based 3DICs (Abstract)

Sabyasachee Banerjee , Department of Computer Science and Engineering, Heritage Institute of Technology, West Bengal, Kolkata 700107
Subhashis Majumder , Department of Computer Science and Engineering, Heritage Institute of Technology, West Bengal, Kolkata 700107
Debesh K. Das , Department of Computer Science and Engineering, Jadavpur University, Jadavpur, Kolkata-32, India
pp. 1-5

Design and simulation of magnetic logic device for next generation data processing (Abstract)

Madhav Rao , International Institute of Information Technology -Bangalore, Bangalore-560100, India
Neha Oraon , International Institute of Information Technology -Bangalore, Bangalore-560100, India
S Ranganatha , International Institute of Information Technology -Bangalore, Bangalore-560100, India
pp. 1-6

A secure architecture for the design for testability structures (Abstract)

Samta D. Talatule , Deptt. of Electronics Engineering, Y.C. College of Engineering, Nagpur, India
Pravin Zode , Deptt. of Electronics Engg., Y.C. College of Engineering, Nagpur, India
Pradnya Zode , Deptt. of Electronics Engg., Y.C. College of Engineering, Nagpur, India
pp. 1-6

Advanced UPF based voltage-aware verification for IOs (Abstract)

Ronak Patel , Institute of Technology, Nirma University, Ahmedabad, India
Amisha Naik , Institute of Technology, Nirma University, Ahmedabad, India
Amit Singh , Design Enablement & Services/CCDS, STMicroelectronics Pvt. Ltd., Greater Noida, India
Archana Arya , Design Enablement & Services/CCDS, STMicroelectronics Pvt. Ltd., Greater Noida, India
Pulkit Bhatnagar , Design Enablement & Services/CCDS, STMicroelectronics Pvt. Ltd., Greater Noida, India
pp. 1-2

Squarer design with reduced area and delay (Abstract)

Arindam Banerjee , Dept. of ECE, JIS College of Engineering, Kalyani, Nadia, West Bengal, India
Debesh Kumar Das , Dept. of CSE, Jadavpur University, Jadavpur, Kolkata-32, West Bengal, India
pp. 1-6

A novel ROPUF for hardware security (Abstract)

Sauvagya Ranjan Sahoo , NIT Rourkela
Sudeendra Kumar , NIT Rourkela
Kamalakanta Mahapatra , NIT Rourkela
pp. 1-2

BONY: An algorithm to generate large synthetic combinational benchmark circuits (Abstract)

Priyankar Talukdar , International Institute of Information Technology, Bangalore
pp. 1-2

Methodology for optimizing ESD protection for high speed LVDS based I/Os (Abstract)

Vishnuram Abhinav , Dept. of Electronics & Electrical Engineering, Indian Institute of Technology, Guwahati, India-781039
Amitabh Chatterjee , Dept. of Electronics & Electrical Engineering, Indian Institute of Technology, Guwahati, India-781039
Dheeraj Kumar Sinha , Dept. of Electronics & Electrical Engineering, Indian Institute of Technology, Guwahati, India-781039
Rajan Singh , Dept. of Electronics & Electrical Engineering, Indian Institute of Technology, Guwahati, India-781039
pp. 1-5

Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell (Abstract)

Rohan Sinha , Department of Electronics and Communications Engineering, IIIT Delhi, New Delhi, India
Pranay Samanta , Department of Electronics and Communications Engineering, IIIT Delhi, New Delhi, India
pp. 1-6

Design of coherence verification unit for heterogeneous CMPs (Abstract)

Bidesh Chakraborty , CSE Department, HIT, Haldia, India
Bhanu Pratap Singh , CSE Department, NIT Durgapur, India
M. Chinnapureddy , CSE Department, NIT Durgapur, India
Mamata Dalui , CSE Department, NIT Durgapur, India
Biplab K Sikdar , CST Department, IIEST Shibpur, India
pp. 1-6

A Hamming code based technique to resolve the bit flip impact on compressed VLSI test data in IP core based SoC (Abstract)

Harikrishna Parmar , ECC Department, C.K. Pithwalla College of Engg & technology, Surat, India
Usha Mehta , ECC Department Nirma University Ahmedabad, India
pp. 1-6

A fault tolerant test hardware for L1 cache module in tile CMPs architecture (Abstract)

Mousumi Saha , Department of Computer Applications National Institute of Technology Durgapur, India
Navneet Kumar Gautam , Department of Computer Applications National Institute of Technology Durgapur, India
Biplab K Sikdar , Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology, Shibpur, India
pp. 1-6

Parallel two step random walk algorithm to analyze VLSI power grid networks (Abstract)

Satyabrata Dash , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati
Vivek Bangera , Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai
Vinay B. Y. Kumar , Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai
Gaurav Trivedi , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati
Sachin B. Patkar , Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai
pp. 1-2

A novel VLSI design of DCTQ processor for FPGA implementation (Abstract)

Yogesh M. Jain , Dept. of Electrical Engineering, VJTI, Mumbai, India
Aviraj R. Jadhav , Dept. of Electrical Engineering, VJTI, Mumbai, India
Harish V. Dixit , Dept. of Electrical Engineering, VJTI, Mumbai, India
Akshay S. Hindole , IIT Bombay, Mumbai, India
Jithin R. Vadakoott , IIT Bombay, Mumbai, India
Devendra S. Bilaye , Dept. of EEE, BITS-Pilani Pilani, India
pp. 1-5

Fault masking in Quantum-dot cellular automata using prohibitive logic circuit (Abstract)

Rajdeep Kumar Nath , CSE Department, National Institute of Technology, Durgapur, India
Bibhash Sen , CSE Department, National Institute of Technology, Durgapur, India
Rachit Daga , CSE Department, National Institute of Technology, Durgapur, India
Nilesh Chakraborty , CSE Department, National Institute of Technology, Durgapur, India
Harsh Tibrewal , CSE Department, National Institute of Technology, Durgapur, India
Biplab K Sikdar , CST Department, Indian Institute of Engineering Science and Technology, Shibpur
pp. 1-5

Sensitivity and non-linearity study and performance enhancement in bossed diaphragm piezoresistive pressure sensor (Abstract)

Ramprasad Nambisan , Department of Electrical & Electronics Engineering, Birla Institute of Technology and Science (BITS), Pilani, Rajasthan, India
S. Santosh Kumar , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani, Rajasthan, India
B. D. Pant , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani, Rajasthan, India
pp. 1-6

High power gain low noise amplifier design for next generation 1–7GHz wideband RF frontend RFIC using 0.18μm CMOS (Abstract)

Hasmukh P Koringa , EC Dept., Government Engineering College, Rajkot, India
Bhushan D. Joshi , Electronics & Communication Engineering, GCET, Vallabh-Vidhyanagar, Anand, India
Vipul Shah , Faculty of IC, Dharmsinh Desai University, Nadiad, India
pp. 1-5

Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT (Abstract)

Govinda Rao Locharla , Department of Electronics and Communications Engineering, National Institute of Technology, Rourkela
K Sudeendra Kumar , Department of Electronics and Communications Engineering, National Institute of Technology, Rourkela
K K Mahapatra , Department of Electronics and Communications Engineering, National Institute of Technology, Rourkela
Samit Ari , Department of Electronics and Communications Engineering, National Institute of Technology, Rourkela
pp. 1-6

An efficient on-chip energy processing circuit for micro-scale energy harvesting systems (Abstract)

Saroj Mondal , Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati, Assam-781039
Roy P. Paily , Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati, Assam-781039
pp. 1-5

Measurement of de-assertion threshold of power-on-reset circuits (Abstract)

Sanjay Kumar Wadhwa , Freescale Semiconductor India Pvt. Ltd., Plot No. 2 and 3, Sector 16A, NOIDA, U.P., India
Avinash Chandra Tripathi , Freescale Semiconductor India Pvt. Ltd., Plot No. 2 and 3, Sector 16A, NOIDA, U.P., India
pp. 1-4

Transient current estimation using S3C (Standard cell current transient characterization) (Abstract)

Michael Skaggs , CSEE Department, University of Maryland, Baltimore County
Sushmita K. Rao , CSEE Department, University of Maryland, Baltimore County
Ryan Robucci , CSEE Department, University of Maryland, Baltimore County
Nilanjan Banerjee , CSEE Department, University of Maryland, Baltimore County
Chintan Patel , CSEE Department, University of Maryland, Baltimore County
pp. 1-6

Molecular modeling of Nano bio p-i-n FET (Abstract)

Debarati Dey , Department of Computer Science & Engineering, West Bengal University of Technology., BF-142, Sector 1, Salt Lake City. Kolkata - 700 064. West Bengal, India
Pradipta Roy , Department of Computer Science & Engineering, West Bengal University of Technology., BF-142, Sector 1, Salt Lake City. Kolkata - 700 064. West Bengal, India
Debashis De , Department of Computer Science & Engineering, West Bengal University of Technology., BF-142, Sector 1, Salt Lake City. Kolkata - 700 064. West Bengal, India
pp. 1-6

Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay (Abstract)

S. G. Pradyumna , Sardar Patel Institute of Technology, Mumbai-400058, India
S. S. Rathod , Sardar Patel Institute of Technology, Mumbai-400058, India
pp. 1-5

TSV aware standard cell placement for 3D ICs (Abstract)

Sameer Pawanekar , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, India
Gaurav Trivedi , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, India
pp. 1-6

Net weighing based timing driven standard cell placer (Abstract)

Sameer Pawanekar , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, India
Gaurav Trivedi , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, India
pp. 1-6

FPGA based disk controller and photon counter of optical polarimeter (Abstract)

Binal B. Baraiya , Department of Electronics and Communication Engineering, CHARUSAT University, Anand (Gujarat), India
Hiren K. Mewada , Department of Electronics and Communication Engineering, CHARUSAT University, Anand (Gujarat), India
Amish B. Shah , Astronomy and Astrophysics Division, Physical Research Laboratory, Ahmedabad (Gujarat), India
pp. 1-6

Out of order floating point coprocessor for RISC V ISA (Abstract)

Vinayak Patil , Centre for Development of Advanced Computing, Bangalore, India
Aneesh Raveendran , Centre for Development of Advanced Computing, Bangalore, India
P M Sobha , Centre for Development of Advanced Computing, Bangalore, India
A David Selvakumar , Centre for Development of Advanced Computing, Bangalore, India
D Vivian , Centre for Development of Advanced Computing, Bangalore, India
pp. 1-7

RISC-V out-of-order data conversion co-processor (Abstract)

Aneesh Raveendran , Centre for Development of Advanced Computing, Bangalore, India
Vinayak Patil , Centre for Development of Advanced Computing, Bangalore, India
Vivian Desalphine , Centre for Development of Advanced Computing, Bangalore, India
P M Sobha , Centre for Development of Advanced Computing, Bangalore, India
A David Selvakumar , Centre for Development of Advanced Computing, Bangalore, India
pp. 1-2

Design and simulative analysis of a batteryless Teflon coated capacitive pressure sensor for glaucoma diagnosis (Abstract)

Y. Mary Asha Latha , Department of Electronics & Communication Engg., NIT Hamirpur, Hamirpur, India
G. Khanna , Department of Electronics & Communication Engg., NIT Hamirpur, Hamirpur, India
pp. 1-5

A 2.47 GHz ultra NanoCrystaline diamond disk resonator with temperature compensation for RF application (Abstract)

Rajesh C Junghare , Centre for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, India
Vinayak Pachkawade , Centre for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, India
Rajendra M Patrikar , Centre for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, India
pp. 1-2

A small bandwidth microelectromechanical ring resonator-based bandpass filter (Abstract)

Vinayak Pachkawade , Centre for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, India
Rajesh Junghare , Centre for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, India
Rajendra Patrikar , Centre for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, India
pp. 1-5

Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors (Abstract)

Prashant Khot , Electronics and Communication, BVBCET, Hubli, India
Rajashekhar B. Shettar , Electronics and Communication BVBCET Hubli, India
pp. 1-5

GA based diagnostic test pattern generation for transition faults (Abstract)

Anupam Bhar , Dept. of Electronics and Electrical Communication, Indian Institute of Technology Kharagpur, India
Santanu Chattopadhyay , Dept. of Electronics and Electrical Communication, Indian Institute of Technology Kharagpur, India
Indranil Sengupta , Dept. of Computer Science and Engineering, Indian Institute of Technology Kharagpur, India
Rohit Kapur , Synopsys Inc., Mountain View, California, USA
pp. 1-6

Side channel attack resistant architecture for elliptic curve cryptography (Abstract)

Pravin Zode , Center for VLSI and Nano Technology, Visvesvaraya National Institute of Technology, Nagpur, India
Raghavendra B. Deshmukh , Center for VLSI and Nano Technology, Visvesvaraya National Institute of Technology, Nagpur, India
pp. 1-2

Detection and analysis of hardware trojan using scan chain method (Abstract)

M Rithesh , VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India
G Harish , VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India
B V Bhargav Ram , VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India
Siva Yellampalli , VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India
pp. 1-6

Low power and hardware cost STUMPS BIST (Abstract)

N Ravi Kiran , VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India
G Harish , VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India
A Karthik , VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India
Siva Yellampalli , VLSI Dept., VTU Extension Centre UTL technologies LTD, Bangalore, India
pp. 1-4

Modified low power scan based technique (Abstract)

M R Gowthami , VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India
G. Harish , VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India
B V Bhargav Ram , VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India
Siva Yellampalli , VLSI Dept., VTU Extension Centre, UTL technologies LTD., Bangalore, India
pp. 1-5

Instruction cache design space exploration for embedded software applications (Abstract)

Rajendra Patel , Electronics & Communication, Engineering Department, MANIT, Bhopal, M.P., India
Arvind Rajawat , Electronics & Communication Engineering Department, MANIT, Bhopal, M.P., India
pp. 1-5

Design and implementation of DVB-S2 transport stream for onboard processing satellite (Abstract)

Rangwani Varsha , Chandubhai. S. Patel Institute of Technology CHARUSAT University, Gujarat, India
Rajat Arora , Onboard Signal Processing Division, Space Applications Centre (SAC) Ahmedabad, Gujarat, India-380015
T V S Ram , Onboard Signal Processing Division, Space Applications Centre (SAC) Ahmedabad, Gujarat, India-380015
Amit Patel , Chandubhai. S. Patel Institute of Technology CHARUSAT University, Gujarat, India
pp. 1-6

Cryptanalysis of hardware based stream ciphers and implementation of GSM stream cipher to propose a novel approach for designing n-bit LFSR stream cipher (Abstract)

Darshana Upadhyay , Department of Computer Science and Technology Nirma Institute of Technology, Ahmedabad, India
Trishla Shah , Department of Computer Science and Technology, Nirma Institute of Technology, Ahmedabad, India
Priyanka Sharma , Department of Computer Science and Technology Nirma Institute of Technology, Ahmedabad, India
pp. 1-6

A new row decoding architecture for fast wordline charging in NOR type Flash memories (Abstract)

Rohan Sinha , Department of Electronics and Communication Engineering, IIIT Delhi, New Delhi, India
Bhawana Singh Nirwan , Department of Electronics and Communication Engineering, IIIT Delhi, New Delhi, India
M. S. Hashmi , Department of Electronics and Communication Engineering, IIIT Delhi, New Delhi, India
pp. 1-5

Fabrication and characterization of pressure sensor, and enhancement of output characteristics by modification of operating pressure range (Abstract)

S. Santosh Kumar , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani, Rajasthan, India
B. D. Pant , CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani, Rajasthan, India
pp. 1-4

Analysis and design guidelines for customized logic families in CMOS (Abstract)

Namrata Singh , Department of Electronics and Communication, IIIT Delhi
Sujay Deb , Department of Electronics and Communication, IIIT Delhi
pp. 1-2

A low-power subthreshold LNA for mobile applications (Abstract)

M M Vinaya , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, Guwahati-781039, India
Roy P. Paily , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, Guwahati-781039, India
Anil Mahanta , Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, Guwahati-781039, India
pp. 1-5

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure (Abstract)

J. G. Pandey , CSIR- Central Electronics Engineering Research Institute Pilani-333031, India
A. Karmakar , CSIR- Central Electronics Engineering Research Institute Pilani-333031, India
C. Shekhar , CSIR- Central Electronics Engineering Research Institute Pilani-333031, India
S. Gurunarayanan , Birla Institute of Technology and Science (BITS) Pilani-333031, India
pp. 1-6

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology (Abstract)

Vijay Savani , EC Department, Institute of Technology, Nirma University
N. M. Devashrayee , EC Department, Institute of Technology, Nirma University
pp. 1-2

An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance (Abstract)

Debasis Dhal , Department of Information Technology, Triguna Sen School of Technology Assam University, Silchar, Cachar - 788 011, Assam, India
Piyali Datta , Department of Computer Science and Engineering, University of Calcutta 92, A. P. C. Road, Kolkata - 700 009, West Bengal, India
Arpan Chakrabarty , Department of Computer Science and Engineering, University of Calcutta 92, A. P. C. Road, Kolkata - 700 009, West Bengal, India
Sudipta Roy , Department of Information Technology, Triguna Sen School of Technology Assam University, Silchar, Cachar - 788 011, Assam, India
Rajat Kumar Pal , Department of Computer Science and Engineering, University of Calcutta 92, A. P. C. Road, Kolkata - 700 009, West Bengal, India
pp. 1-6

An all digital delay lock loop architecture for high precision timing generator (Abstract)

Mohammad Waris , Sensors Electronics Group, Sensors Development Area, Space Application Centre, Ahmedabad, India
Urvi Mehta , Institute of Technology, Nirma University, Ahmedabad, India
Rajiv Kumaran , Sensors Electronics Group, Sensors Development Area, Space Application Centre, Ahmedabad, India
Sanjeev Mehta , Sensors Electronics Group, Sensors Development Area, Space Application Centre, Ahmedabad, India
Arup Roy Chowdhury , Sensors Electronics Group, Sensors Development Area, Space Application Centre, Ahmedabad, India
pp. 1-6

Verilog-A implementation of energy-efficient SAR ADCs for biomedical application (Abstract)

M. Santhanalakshmi , ECE Department, PSG College of Technology, Coimbatore, India
K. Yasoda , ECE Department, PSG College of Technology, Coimbatore, India
pp. 1-6

Novel design for wideband piezoelectric vibrational energy harvester (P-VEH) (Abstract)

Shaurya Kaushal , Department of Mechanical Engineering, Birla Institute of Technology and Science, Pilani, India 333031
Pulkit Kumar Dubey , Department of Mechanical Engineering, Birla Institute of Technology and Science, Pilani, India 333031
Gaurav Prabhudesai , Department of Mechanical Engineering, Birla Institute of Technology and Science, Pilani, India 333031
B. D. Pant , MEMS and Microsensors Group, CSIR-Central Electronics Engineering Research Institute, Pilani, India 333031
pp. 1-5

Standby leakage current estimation model for multi threshold CMOS inverter circuit in deep submicron technology (Abstract)

Hari Sarkar , Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata, India
Sudakshina Kundu , Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata, India
pp. 1-6

Multi terminal net routing for island style FPGAs using nearly-2-SAT computation (Abstract)

Shyamapada Mukherjee , Computer Science and Engineering, National Institute of Technology, Durgapur, India
Suchismita Roy , Computer Science and Engineering, National Institute of Technology, Durgapur, India
pp. 1-6

Implementation of a high speed multiplier for high-performance and low power applications (Abstract)

G Ganesh Kumar , Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, India, 500078
Subhendu K Sahoo , Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, India, 500078
pp. 1-4

A novel two phase heuristic routing technique in digital microfluidic biochip (Abstract)

Sarit Chakraborty , B.P. Poddar Institute of Management and Technology, Kolkata, India
Chandan Das , Dr. B. C. Roy Engineering college, Durgapur
Susanta Chakraborty , Indian Institute of Engineering Science and Technology
Parthasarathi Dasgupta , Indian Institute of Management, Calcutta, India
pp. 1-6

A pipelined memory-efficient architecture for face detection and tracking on a multicore environment (Abstract)

N. Sudha , XMOS Semiconductor India Pvt. Ltd., Chennai, India
D. Bharat Chandrahas , Indian Institute of Technology Madras, Chennai, India
pp. 1-2

Performance study of side block oxide band gap engineered SONOS: A device simulation approach (Abstract)

Gagan Deep Verma , ABV-Indian Institute of Information Technology and Management, Gwalior, Madhya Pradesh, India - 474015
Manisha Pattanaik , ABV-Indian Institute of Information Technology and Management, Gwalior, Madhya Pradesh, India - 474015
pp. 1-4

A constructive heuristic for application mapping onto an express channel based Network-on-Chip (Abstract)

Sandeep D'souza , Indian Institute of Technology Kharagpur, Kharagpur, India
J. Soumya , National Institute of Technology Goa, Farmagudi, India
Santanu Chattopadhyay , Indian Institute of Technology Kharagpur, Kharagpur, India
pp. 1-6

Particle swarm optimization approach for low temperature BIST (Abstract)

Arpita Dutta , Dept. of Electronics and Electrical Communication, Indian Institute of Technology Kharagpur, India
Santanu Chattopadhyay , Dept. of Electronics and Electrical Communication, Indian Institute of Technology Kharagpur, India
pp. 1-6

Designing efficient combinational compression architecture for testing industrial circuits (Abstract)

A. Chandra , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA, 94043, USA
S. Kulkarni , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA, 94043, USA
S. Chebiyam , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA, 94043, USA
R. Kapur , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA, 94043, USA
pp. 1-6

Low power, high speed error tolerant multiplier using approximate adders (Abstract)

K. Manikantta Reddy , Department of Electronics and Communications, National Institute of Technology Goa, India
Y. B. Nithin Kumar , Department of Electronics and Communications, National Institute of Technology Goa, India
Dheeraj Sharma , Department of Electronics and Communications, National Institute of Technology Goa, India
M. H. Vasantha , Department of Electronics and Communications, National Institute of Technology Goa, India
pp. 1-6

Low-leakage architecture for embedded ROM (Abstract)

Mansi S. Masrani , Post-Graduation and Research Department, Nirma University, Ahmedabad, India
Raghavendra Chilukuri , DTS CMO team, Intel Technologies India Pvt. Ltd., Bengaluru, India
pp. 1-2

A methodology to reuse random IP stimuli in an SoC functional verification environment (Abstract)

V S Rashmi , Texas Instruments (India) Pvt. Ltd., Bengaluru, India
Giridhar Somayaji , Lantiq Semiconductors Asia, Singapore
Sirisha Bhamidipathi , Juniper Networks, California, USA
pp. 1-5

Author index (PDF)

pp. 1-7

Cover page (PDF)

pp. 1

Keyword index (PDF)

pp. 1-11

Preface (PDF)

pp. v-xix

Introduction to MEMS; their applications as sensors for chemical & bio sensing (PDF)

Nitin S. Kale , Nanosniff Technologies Pvt Ltd, M-01 SINE CSRE Bldg, IIT Bombay, Powai, Mumbai - 400076
pp. 1-2

Multicore processor — Architecture and programming (PDF)

N. Sudha , XMOS Semiconductor Ltd, Chennai, Tamil Nadu, India
pp. 1-2

Network-on-chip: Current issues and challenges (PDF)

Manoj Singh Gaur , Computer Engineering, Malaviya National Institute of Technology MNIT, Jaipur, India
Vijay Laxmi , Computer Engineering, Malaviya National Institute of Technology MNIT, Jaipur, India
Mark Zwolinski , Electronic Systems Design Group University of Southampton, High field, Southampton SO17 1BJ
Manoj Kumar , Malaviya National Institute of Technology MNIT, Jaipur, India
Niyati Gupta , Malaviya National Institute of Technology MNIT, Jaipur, India
Ashish , Malaviya National Institute of Technology MNIT, Jaipur, India
pp. 1-3

Power- and thermal-aware testing of VLSI circuits and systems (PDF)

Santanu Chattopadhyay , Dept. of Electronics and Electrical Communication Engg., Indian Institute of Technology Kharagpur, West Bengal, India - 721302
pp. 1

Real-time embedded systems analysis — From theory to practice (PDF)

Ansuman Banerjee , Advanced Computing and Microelectronics Unit, Indian Statistical Institute
Arijit Mondal , Dept. of Computer Science & Engineering, Indian Institute of Technology, Patna, Bihar, India
Arnab Sarkar , Dept. of Computer Science & Engineering, Indian Institute of Technology, Guwahati, Assam, India
Santosh Biswas , Dept. of Computer Science & Engineering, Indian Institute of Technology, Guwahati Assam, India
pp. 1-2

SCL 180nm CMOS foundry: High reliability ASIC design for aerospace applications (PDF)

Shri H. S. Jatana , Semi-Conductor Laboratory (SCL), Chandigarh
Nilesh M. Desai , MRSA, Space Applications Centre (ISRO), Ahmedabad
pp. 1-2

Technology scaling and its side effects (PDF)

Aminul Islam , Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India 835215
pp. 1
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