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2015 19th International Symposium on VLSI Design and Test (VDAT) (2015)
Ahmedabad, India
June 26, 2015 to June 29, 2015
ISBN: 978-1-4799-1742-6
pp: 1-6
Arindam Banerjee , Dept. of ECE, JIS College of Engineering, Kalyani, Nadia, West Bengal, India
Debesh Kumar Das , Dept. of CSE, Jadavpur University, Jadavpur, Kolkata-32, West Bengal, India
ABSTRACT
Digital multiplier and squarer circuits are indispensable in Digital signal processing and cryptography. In many mathematical computations, squaring and cubing are frequently used. Generally the multiplier is used in computing square. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage that we can avoid the generation of many partial products by eliminating the redundant bits, thus resulting the circuit to be simpler with less hardware, propagation delay and power consumption. Our work proposes an efficient algorithm for squaring techniques with less hardware cost. We have used literals minimization technique to achieve our design. This technique compares favourably with the recent work [1] in this area.
INDEX TERMS
Logic gates, Delays, Adders, Vegetation, Optimization, Hardware, Field programmable gate arrays
CITATION

A. Banerjee and D. K. Das, "Squarer design with reduced area and delay," 2015 19th International Symposium on VLSI Design and Test (VDAT), Ahmedabad, India, 2015, pp. 1-6.
doi:10.1109/ISVDAT.2015.7208092
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