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Computer Modeling and Simulation, International Conference on (2009)
Mar. 25, 2009 to Mar. 27, 2009
ISBN: 978-0-7695-3593-7
pp: 574-578
This paper presents an integrated modeling, simulation and analysis technique for high-speed serial link transceiver over band-limited channel. The Verilog-A behavioral modeling blocks, transistor-level circuits based on the BSIM models, and the backplane channel with .s4p format model were simulated simultaneously in Cadence Spectre environment. The output data were post-processed with Matlab for performance analysis. Compared with HDL-based modeling scheme and event-driven modeling method, the proposed modeling method provides the effective system level verification in the integrated environment, even with real transistor-level circuits included.
wireline transceiver; backplane transmission; SerDes; DFE; equalization; modeling; verilog-A; High-speed I/O;
Bo Wang, Dianyong Chen, Bangli Liang, Tad Kwasniewski, Jinguang Jiang, "Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel", Computer Modeling and Simulation, International Conference on, vol. 00, no. , pp. 574-578, 2009, doi:10.1109/UKSIM.2009.87
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