Seventh International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC'05) (2005)
Sept. 25, 2005 to Sept. 29, 2005
Srivastav Sethupathy , OSU
Nohpill Park , OSU
Marcin Paprzycki , SWPS
In this paper we apply integer programming (IP) based techniques to the problem of delay balancing in wave-pipelined circuits. The proposed approach considers delays, as well as fan-in and fan-out associated with every node in the circuit. After a weighted graph representation of the circuit is formed a node collapsing procedure is used to preprocess (reduce the size of) the system and to obtain the final formulation of the IP problem, which is solved by using a branch and bound heuristic to acquire a minimum delay in the circuit. We also compare the proposed technique with application — to the same problem — of a linear programming solver.
M. Paprzycki, S. Sethupathy and N. Park, "Logic Restructuring for Delay Balancing in Wave-Pipelined Circuits: An Integer Programming Approach," Seventh International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC'05)(SYNASC), Timisoara, Romania, 2005, pp. 182-188.