Secure Software Integration and Reliability Improvement Companion, IEEE International Conference on (2010)
June 9, 2010 to June 11, 2010
VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study.
Test case generation, model checking, synthesizable VHDL, program transformation, timed automata
T. Ayav, F. Belli and T. Tuglular, "Towards Test Case Generation for Synthesizable VHDL Programs Using Model Checker," Secure Software Integration and Reliability Improvement Companion, IEEE International Conference on(SSIRI-C), Singapore, Singapore, 2010, pp. 46-53.