2015 IEEE Symposium on Security and Privacy (SP) (2015)
San Jose, CA, USA
May 17, 2015 to May 21, 2015
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/SP.2015.9
CHERI extends a conventional RISC Instruction-Set Architecture, compiler, and operating system to support fine-grained, capability-based memory protection to mitigate memory-related vulnerabilities in C-language TCBs. We describe how CHERI capabilities can also underpin a hardware-software object-capability model for application compartmentalization that can mitigate broader classes of attack. Prototyped as an extension to the open-source 64-bit BERI RISC FPGA soft-core processor, Free BSD operating system, and LLVM compiler, we demonstrate multiple orders-of-magnitude improvement in scalability, simplified programmability, and resulting tangible security benefits as compared to compartmentalization based on pure Memory-Management Unit (MMU) designs. We evaluate incrementally deployable CHERI-based compartmentalization using several real-world UNIX libraries and applications.
data protection, operating systems (computers), program compilers, reduced instruction set computing, software architecture
R. N. Watson et al., "CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization," 2015 IEEE Symposium on Security and Privacy (SP), San Jose, CA, USA, 2015, pp. 20-37.