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ABSTRACT
Memory bandwidth is a major limiting factor in the scalability of parallel iterative algorithms that rely on sparse matrix-vector multiplication (SpMV). This paper introduces Hierarchical Diagonal Blocking (HDB), an approach which we believe captures many of the existing optimization techniques for SpMV in a common representation. Using this representation in conjuction with precision-reduction techniques, we develop and evaluate high-performance SpMV kernels. We also study the implications of using our SpMV kernels in a complete iterative solver. Our method of choice is a Combinatorial Multigrid solver that can fully utilize our fastest reduced-precision SpMV kernel without sacrificing the quality of the solution. We provide extensive empirical evaluation of the effectiveness of the approach on a variety of benchmark matrices, demonstrating substantial speedups on all matrices considered.
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CITATION

G. E. Blelloch, G. L. Miller, I. Koutis and K. Tangwongsan, "Hierarchical Diagonal Blocking and Precision Reduction Applied to Combinatorial Multigrid," 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis(SC), New Orleans, LA, 1899, pp. 1-12.
doi:10.1109/SC.2010.29
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