The Community for Technology Leaders
SC Conference (2003)
Phoenix, Arizona
Nov. 15, 2003 to Nov. 21, 2003
ISBN: 1-58113-695-1
pp: 22
Keith D. Underwood , Sandia National Laboratories, Albuquerque, NM
Ron Sass , Clemson University, SC
Ranjesh G. Jaganathan , Clemson University, SC
ABSTRACT
The high overhead of generic protocols like TCP/IP provides strong motivation for the development of a better protocol architecture for cluster-based parallel computers. Reconfigurable computing has a unique opportunity to contribute hardware level protocol acceleration while retaining the flexibility to adapt to changing needs. Specifically, applications on a cluster have various quality of service needs. In addition, these applications typically run for a long time relative to the reconfiguration time of an FPGA. Thus, it is possible to provide application-specific protocol processing to improve performance and reduce space utilization. Reducing space utilization permits the use of a greater portion of the FPGA for other application-specific processing.<div></div> This paper focuses on work to create a set of parameterizable components that can be put together as needed to obtain a customized protocol for each application. To study the feasibility of such an architecture, hardware components were built that can be stitched together as needed to provide the required functionality. Feasibility is demonstrated using four different protocol configurations, namely: (1) unreliable packet transfer; (2) reliable, unordered message transfer without duplicate elimination; (3) reliable, unordered message transfer with duplicate elimination; and (4) reliable, ordered message transfer with duplicate elimination. The different configurations illustrate trade-offs between chip space and functionality.
INDEX TERMS
Intelligent Network Interface Card, reconfigurable computing, networking protocols, cluster computing
CITATION
Keith D. Underwood, Ron Sass, Ranjesh G. Jaganathan, "A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC", SC Conference, vol. 00, no. , pp. 22, 2003, doi:10.1109/SC.2003.10005
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