The Community for Technology Leaders
SC Conference (1995)
San Diego, California
Dec. 3, 1995 to Dec. 6, 1995
ISBN: 0-89791-816-9
pp: 61
Leonidas I. Kontothanassis , University of Rochester
Michael L. Scott , University of Rochester
Ricardo Bianchini , University of Rochester
ABSTRACT
Release consistency is a widely accepted memory model for distributed shared memory systems. Eager release consistency represents the state of the art in release consistent protocols for hardware-coherent multiprocessors, while lazy release consistency has been shown to provide better performance for software distributed shared memory (DSM). Several of the optimizations performed by lazy protocols have the potential to improve the performance of hardware-coherent multiprocessors as well, but their complexity has precluded a hardware implementation. With the advent of programmable protocol processors it may become possible to use them after all. We present and evaluate a lazy release-consistent protocol suitable for machines with dedicated protocol processors. This protocol admits multiple concurrent writers, sends write notices concurrently with computation, and delays invalidations until acquire operations. We also consider a lazier protocol that delays sending write notices until release operations. Our results indicate that the first protocol outperforms eager release consistency by as much as 20% across a variety of applications. The lazier protocol, on the other hand, is unable to recoup its high synchronization overhead. This represents a qualitative shift from the DSM world, where lazier protocols always yield performance improvements. Based on our results, we conclude that machines with flexible hardware support for coherence should use protocols based on lazy release consistency, but in a less ''aggressively lazy'' form than is appropriate for DSM.
INDEX TERMS
Cache Coherence, Lazy Release Consistency, Protocol Processors, Shared Memory
CITATION

R. Bianchini, M. L. Scott and L. I. Kontothanassis, "Lazy Release Consistency for Hardware-Coherent Multiprocessors," SC Conference(SC), San Diego, California, 1995, pp. 61.
doi:10.1109/SUPERC.1995.43
88 ms
(Ver 3.3 (11022016))