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SBCCI 2005. 18th Symposium on Integrated Circuits and Systems Design (2005)
Florianopolis
Sept. 4, 2005 to Sept. 7, 2005
ISBN: 1-59593-174-0
TABLE OF CONTENTS

[Cover] (PDF)

pp. C1

Copyright page (PDF)

pp. ii

Table of contents (PDF)

pp. v-viii

list-reviewer (PDF)

pp. xii-xiii

Advanced Power Management of SoC Platforms (PDF)

Luca Benini , Senior Member, IEEE, Associate Professor, Department of Electrical Engineering and Computer Science (DEIS), Universita di Bologna, Bologna, Italy. Ibenini@deis.unibo.it
pp. 1

A Design Methodology for Analogue CMOS Circuits (PDF)

Paul L. Jespers , Emeritus Professor, Université Catholique de Louvain, Louvain-la-Neuve, Belgium. Jespers@dice.uci.ac.be
pp. 2

The Process of Higher Level Design (PDF)

John Sanguinetti , CTO, Founder, Forte Design Systems, San Jose, CA, USA. jws@forteds.com
pp. 3

Technology and Architecture for Deep Submicron RF CMOS Technology (PDF)

Abdelkarim Mercha , IMEC, Leuven, Belgium. Abdelkarim.Mercha@imec.be
pp. 4

High Level Design: The Future is Now (PDF)

John Sanguinetti , CTO, Founder, Forte Design Systems, San Jose, CA, USA. jws@forteds.com
pp. 5

Energy Efficient NoC Design (PDF)

Luca Benini , Associate Professor, Senior Member, IEEE, Department of Electrical Engineering (DEIS), Università di Bologna, Bologna, Italy. Ibenini@deis.unibo.it
pp. 6

A Survey of Multistep A to D Converters and Error Correction Mechanisms (PDF)

Paul L. Jespers , Emeritus Professor, Université Catholique de Louvain, Louvain-la-Neuve, Belgium. Jespers@dice.ucl.ac.be
pp. 7

IC Design Requirements for Automotive Applications (PDF)

Armando G. da Silva , Freescale Semiconductors Brazil, Jaguariúna, SP, Brazil. armando.gomes@freescale.com
pp. 8

EMC-EMI Optimized High Speed CAN Line Driver (PDF)

Armando Gomes , Freescale Semiconductors, Rod. SP-340, km. 128,7 A, Jaguariuna, Brazil. Phone: +55-19-3847-8239, Armando.Gomes@freescale.com
Edevaldo Pereira S. Junior , Freescale Semiconductors, Rod. SP-340, km. 128,7 A, Jaguariuna, Brazil. Phone: +55-19-3847-8136, Edevaldo.Pereira@freescale.com
Ivan Nascimento , Freescale Semiconductors, Rod. SP-340, km. 128,7 A, Jaguariuna, Brazil. Phone: +55-19-3847-8319, Ivan.Nascimento@freescale.com
pp. 9-14

On the Design of Very Small Transconductance OTAs with Reduced Input Offset (PDF)

Alfredo Arnaud , DIE Universidad Católica, 8 de Octubre 2738, Montevideo - Uruguay. +598-2 4872717-ext.407, email: aarnaud@ucu.edu.uy
Rafaella Fiorelli , GME-IIE Univ.de la República, Julio Herrera y Reissig 565/lIE, Montevideo - Uruguay. +598-2 7110974 - ext. 123, email: fiorelli@fing.edu.uy
Carlos Galup-Montoro , LCI-EEL Univ.Fed. de Santa Catarina, 88040-900 Florianópolis - SC, Brazil. +55 48 331 9280, email: carlos@eel.ufsc.br
pp. 15-20

T-Shaped Association of Transistors: Modeling of Multiple Channel Lengths and Regular Associations (PDF)

Alessandro Girardi , Federal University of Rio Grande do Sul - UFRGS, Informatics Institute, Caixa Postal 15.064 - Zip 91.501-970, Porto Alegre-RS, Brazil. girardi@inf.ufrgs.br
Fernando P. Cortes , Federal University of Rio Grande do Sul - UFRGS, Informatics Institute, Caixa Postal 15.064 - Zip 91.501-970, Porto Alegre-RS, Brazil. fpcortes@inf.ufrgs.br
Eduardo Conrad , Federal University of Rio Grande do Sul - UFRGS, Informatics Institute, Caixa Postal 15.064 - Zip 91.501-970, Porto Alegre-RS, Brazil. econradjr@inf.ufrgs.br
Sergio Bampi , Federal University of Rio Grande do Sul - UFRGS, Informatics Institute, Caixa Postal 15.064 - Zip 91.501-970, Porto Alegre-RS, Brazil. bampi@inf.ufrgs.br
pp. 21-26

On the Adequate Transistor Modeling for Optimal Design of CMOS OTA (PDF)

E.P. Santana , Laboratório de Concepção de Circuitos Integrados, Departamento de Engenharia Elétrica, Universidade Federal da Bahia, Rua Aristides Novis 2, Federação, Salvador - BA, Brazil CEP 40210-630. ecoluzed@ig.com.br
N.R. Ferreira , Laboratório de Concepção de Circuitos Integrados, Departamento de Engenharia Elétrica, Universidade Federal da Bahia, Rua Aristides Novis 2, Federação, Salvador - BA, Brazil CEP 40210-630. niraldo@ufba.br
C.E.T. Dorea , Laboratório de Concepção de Circuitos Integrados, Departamento de Engenharia Elétrica, Universidade Federal da Bahia, Rua Aristides Novis 2, Federação, Salvador - BA, Brazil CEP 40210-630. cetdorea@ufba.br
A. I. A. Cunha , Laboratório de Concepção de Circuitos Integrados, Departamento de Engenharia Elétrica, Universidade Federal da Bahia, Rua Aristides Novis 2, Federação, Salvador - BA, Brazil CEP 40210-630. aiac@ufba.br
pp. 27-31

Fundamentals of Next Generation Compact MOSFET Models (PDF)

C. Galup-Montoro , carlos@eel.ufsc.br
Marcio C. Schneider , Universidade Federal de Santa, Catarina, Campus Trindade - CTC-EEL-LCI, Florianopolis-SC- Brazil. +55-48-331-7720, marcio@eel.ufsc.br
Viriato C. Pahim , viriato@grad.ufsc.br
pp. 32-37

Improving Run Times by Pruned Application of Synthesis Transforms (PDF)

Renato F. Hentschke , IBM Research, 1101 Kitchawan Rd. Yorktown Heights, NY 10598; Universidade Federal do Rio Grande do Sul - Av. Bento Gonqalves, 9500. Bloco IV. CP 15064 CEP 91501-970 Porto Alegre Brazil. +55-51 84079005, renato@inf.ufrgs.br
Jagannathan Narasimhan , IBM Research, 1101 Kitchawan Rd. Yorktown Heights, NY 10598. (914)-945-1550, jagan@us.ibm.com
David Kung , IBM Research, 1101 Kitchawan Rd. Yorktown Heights, NY 10598. (914) 945-3183, kung@us.ibm.com
pp. 38-43

An Efficient Subcircuit Recognition Using the Nonlinear Graph Matching (PDF)

Nikolay Rubanov , Magma Design Automation, 5460 Bayfront Plaza, Santa Clara, CA, 95054. rnsdsp@hotmail.com
pp. 44-49

Task Scheduling for Power Optimisation of Multi Frequency Synchronous Data Flow Graphs (PDF)

Bastian Knerr , Institute for Communications and RF Engineering, University of Technology, Vienna, Austria. bknerr@nt.tuwien.ac.at
Martin Holzer , Institute for Communications and RF Engineering, University of Technology, Vienna, Austria. mholzer@nt.tuwien.ac.at
Markus Rupp , Institute for Communications and RF Engineering, University of Technology, Vienna, Austria. mrupp@nt.tuwien.ac.at
pp. 50-55

Miriã_SI: A Tool for the Synthesis of Speed-Independent Multi Burst-Mode Controllers (PDF)

Duarte Lopes de Oliveira , Instituto Tecnológico de Aeronáutica - IEEA - ITA., Praça Marechal Eduardo Gomes, 50 - CEP 12228-900 - SJC - São Paulo - Brazil. +55(12)3947-6813, duarte@ita.br
Marius Strum , Laboratório de Microeletrônica da Escola Politécnica da USP, Av. Prof. Luciano Gualberto, Trav 3, 158 - CEP 05508-900 - São Paulo - SP - Brazil. +55(11)3091-5310, strum@lme.usp.br
Wang Jiang Chau , Laboratório de Microeletrônica da Escola Politécnica da USP, Av. Prof. Luciano Gualberto, Trav 3, 158 - CEP 05508-900 - São Paulo - SP - Brazil. +55(11)3091-5310, jcwang@lme.usp.br
pp. 56-61

Evaluating Fault Coverage of Bulk Built-in Current Sensor for Soft Errors in Combinational and Sequential Logic (PDF)

Egas Henes Neto , Universidade Estadual do Rio Grande do Sul, Engenharia em Sistemas Digitais, Estrada Santa Maria 2300, Guaiba - RS - Brazil. +55 51 491 40 42, egas-henes@uergs.edu.br
Ivandro Ribeiro , Universidade Estadual do Rio Grande do Sul, Engenharia em Sistemas Digitais, Estrada Santa Maria 2300, Guaiba - RS - Brazil. +55 51 491 40 42, ivandro-ribeiro@uergs.edu.br
Michele Vieira , Universidade Estadual do Rio Grande do Sul, Engenharia em Sistemas Digitais, Estrada Santa Maria 2300, Guaiba - RS - Brazil. +55 51 491 40 42, michele-vieira@uergs.edu.br
Gilson Wirth , Universidade Estadual do Rio Grande do Sul, Engenharia em Sistemas Digitais, Estrada Santa Maria 2300, Guaiba - RS - Brazil. +55 51 491 40 42, gilson-wirth@uergs.edu.br
Fernanda Lima Kastensmidt , Universidade Federal do Rio Grande do Sul, PPGC - Instituto de Informatica, Caixa Postal: 15064, Porto Alegre - RS - Brazil. +55 51 33 16 70 36, fglima@inf.ufrgs.br
pp. 62-67

A Constraint-Based Solution for On-Line Testing of Processors Embedded in Real-Time Applications (PDF)

Marcelo Moraes , PPGC - Instituto de lnformática, UFRGS, Av. Bento Gonçalves, 9500 - Bloco IV, 91501-970 Porto Alegre - Brazil. +55 51 3316-6161, msmoraes@inf.ufrgs.br
Erika Cota , PPGC - Instituto de lnformática, UFRGS, Av. Bento Gonçalves, 9500 - Bloco IV, 91501-970 Porto Alegre - Brazil. +55 51 3316-6161, erika@inf.ufrgs.br
Luigi Carro , PPGC - Instituto de lnformática, UFRGS, Av. Bento Gonçalves, 9500 - Bloco IV, 91501-970 Porto Alegre - Brazil. +55 51 3316-6161; PPGEE - Depto. Energia Elétrica, UFRGS, Av. Osvaldo Aranha, 103, 90035-190 Porto Alegre - Brazil. +55 51 3316-3515, carro@eletro.ufrgs.br
Flavio Wagner , PPGC - Instituto de lnformática, UFRGS, Av. Bento Gonçalves, 9500 - Bloco IV, 91501-970 Porto Alegre - Brazil. +55 51 3316-6161, flavio@inf.ufrgs.br
Marcelo Lubaszewski , PPGC - Instituto de lnformática, UFRGS, Av. Bento Gonçalves, 9500 - Bloco IV, 91501-970 Porto Alegre - Brazil. +55 51 3316-6161; PPGEE - Depto. Energia Elétrica, UFRGS, Av. Osvaldo Aranha, 103, 90035-190 Porto Alegre - Brazil. +55 51 3316-3515, luba@eletro.ufrgs.br
pp. 68-73

Automatic Generation of Test Sets for SBST of Microprocessor IP Cores (PDF)

E. Sanchez , Politecnico di Torino, Dip. di Automatica e Informatica, Corso Duca degli Abruzzi 24. 10129, Torino, Italy. Tel: +39-011564.7092, Fax: +39-011564.7099, edgar.sanchez@polito.it
M. Sonza Reorda , Politecnico di Torino, Dip. di Automatica e Informatica, Corso Duca degli Abruzzi 24. 10129, Torino, Italy. Tel: +39-011564.7092, Fax: +39-011564.7099, matteo.sonzareorda@polito.it
G. Squillero , Politecnico di Torino, Dip. di Automatica e Informatica, Corso Duca degli Abruzzi 24. 10129, Torino, Italy. Tel: +39-011564.7092, Fax: +39-011564.7099, giovanni.squillero@polito.it
M. Violante , Politecnico di Torino, Dip. di Automatica e Informatica, Corso Duca degli Abruzzi 24. 10129, Torino, Italy. Tel: +39-011564.7092, Fax: +39-011564.7099, massimo.violante@polito.it
pp. 74-79

Going Beyond TMR for Protection Against Multiple Faults (PDF)

C. A. L. Lisboa , Instituto de Informática, Av. Bento Gonçalves, 9500, Bloco IV, 91501-970 - Porto Alegre, RS, Brasil. +55 51 3316 7748, calisboa@inf.ufrgs.br
E. Schuler , Depto. de Engenharia Elétrica, Av. Osvaldo Aranha, 103/206-B, 90035-190 - Porto Alegre, RS, Brasil. +55 51 3316 3516, eschuler@eletro.ufrgs.br
Luigi Carro , Depto. de Engenharia Elétrica, Av. Osvaldo Aranha, 103/206-B, 90035-190 - Porto Alegre, RS, Brasil. +55 51 3316 3516, carro@eletro.ufrgs.br
pp. 80-85

Arithmetic-Based Address Translation for Energy-Efficient Virtual Memory Support in Low-Power, Real-Time Embedded Systems (PDF)

Xiangrong Zhou , University of Maryland, College Park, USA. xrzhou@glue.umd.edu
Peter Petrov , University of Maryland, College Park, USA. ppetrov@ece.umd.edu
pp. 86-91

Exploiting Java Through Binary Translation for Low Power Embedded Reconfigurable Systems (PDF)

Antonio Carlos S. Beck , Universidade Federal do Rio Grande do Sul, Instituto de Informática - Av. Bento Gonçalves, 9500 Campus do Vale - Porto Alegre, Brasil. caco@inf.ufrgs.br
Victor F. Gomes , Universidade Federal do Rio Grande do Sul, Instituto de Informática - Av. Bento Gonçalves, 9500 Campus do Vale - Porto Alegre, Brasil. vfgomes@inf.ufrgs.br
Luigi Carro , Universidade Federal do Rio Grande do Sul, Instituto de Informática - Av. Bento Gonçalves, 9500 Campus do Vale - Porto Alegre, Brasil. carro@inf.ufrgs.br
pp. 92-97

A Time Petri Net Based Approach for Embedded Hard Real-Time Software Synthesis with Multiple Operational Modes (PDF)

Eduardo Tavares , Centro de Informática, Universidade Federal de Pernambuco, 50732-970 PO Box 7851 Recife-Brazil. eagt@cin.ufpe.br
Paulo Maciel , Centro de Informática, Universidade Federal de Pernambuco, 50732-970 PO Box 7851 Recife-Brazil. prmm@cin.ufpe.br
Arthur Bessa , Centro de Informática, Universidade Federal de Pernambuco, 50732-970 PO Box 7851 Recife-Brazil. arthur.bessa@fucapi.br
Raimundo Barreto , Centro de Informática, Universidade Federal de Pernambuco, 50732-970 PO Box 7851 Recife-Brazil. rsb@cin.ufpe.br
Leonardo Barros , Centro de Informática, Universidade Federal de Pernambuco, 50732-970 PO Box 7851 Recife-Brazil. lab2@cin.ufpe.br
Meuse Oliveira , Escola Politécnica, Universidade de Pernambuco, 50751-460 Praça Internacional Recife-Brazil. mnoj@cin.ufpe.br
Ricardo Lima , Escola Politécnica, Universidade de Pernambuco, 50751-460 Praça Internacional Recife-Brazil. ricardo@upe.poli.br
pp. 98-103

Making Object Oriented Efficient for Embedded System Applications (PDF)

Julio C. B. Mattos , Federal University of Rio Grande do Sul, Informatics Institute, Porto Alegre - RS - Brasil. julius@inf.ufrgs.br
Emilena Specht , Federal University of Rio Grande do Sul, Informatics Institute, Porto Alegre - RS - Brasil. emilenas@inf.ufrgs.br
Bruno Neves , Federal University of Rio Grande do Sul, Informatics Institute, Porto Alegre - RS - Brasil. bsneves@inf.ufrgs.br
Luigi Carro , Federal University of Rio Grande do Sul, Electrical Engineering Dept., Porto Alegre - RS - Brasil. carro@eletro.ufrgs.br
pp. 104-109

Design of a Decompressor Engine on a SPARC Processor (PDF)

E. Billo , IC-UNICAMP, Caixa Postal 6176, 13084-971 Campinas/SP Brazil. +55 19 3788 5838, eduardo.billo@ic.unicamp.br
R. Azevedo , IC-UNICAMP, Caixa Postal 6176, 13084-971 Campinas/SP Brazil. +55 19 3788 5838, rodolfo@ic.unicamp.br
G. Araujo , IC-UNICAMP, Caixa Postal 6176, 13084-971 Campinas/SP Brazil. +55 19 3788 5838, guido@ic.unicamp.br
P. Centoducatte , IC-UNICAMP, Caixa Postal 6176, 13084-971 Campinas/SP Brazil. +55 19 3788 5838, ducatte@ic.unicamp.br
E. Wanderley Netto , GEINF CEFET-RN, Sen Salgado Filho, 1559, 59015-000 Natal/RN Brazil. +55 84 4005 2637, braulio@cefetrn.br
pp. 110-114

Current Mask Generation: A Transistor Level Security Against DPA Attacks (PDF)

Daniel Mesquita , LIRMM - Laboratoire d'Informatique, de Robotique et, de Microélectronique de Montpellier, Université Montpellier 11, 161 rue Ada - CEDEX 5 - 34392 - Montpellier - France. Phone: +33 4 67 41 85 69, mesquita@lirmm.fr
Jean-Denis Techer , LIRMM - Laboratoire d'Informatique, de Robotique et, de Microélectronique de Montpellier, Université Montpellier 11, 161 rue Ada - CEDEX 5 - 34392 - Montpellier - France. Phone: +33 4 67 41 85 69, techer@lirmm.fr
Lionel Torres , LIRMM - Laboratoire d'Informatique, de Robotique et, de Microélectronique de Montpellier, Université Montpellier 11, 161 rue Ada - CEDEX 5 - 34392 - Montpellier - France. Phone: +33 4 67 41 85 69, torres@lirmm.fr
Gilles Sassatelli , LIRMM - Laboratoire d'Informatique, de Robotique et, de Microélectronique de Montpellier, Université Montpellier 11, 161 rue Ada - CEDEX 5 - 34392 - Montpellier - France. Phone: +33 4 67 41 85 69, sassatelli@lirmm.fr
Gaston Cambon , LIRMM - Laboratoire d'Informatique, de Robotique et, de Microélectronique de Montpellier, Université Montpellier 11, 161 rue Ada - CEDEX 5 - 34392 - Montpellier - France. Phone: +33 4 67 41 85 69, cambon@lirmm.fr
Michel Robert , LIRMM - Laboratoire d'Informatique, de Robotique et, de Microélectronique de Montpellier, Université Montpellier 11, 161 rue Ada - CEDEX 5 - 34392 - Montpellier - France. Phone: +33 4 67 41 85 69, robert@lirmm.fr
Fernando Moraes , FACIN - Faculdade de Informática, Pontifícia Universidade Católica do Rio Grande do Sul, Av. Ipiranga, 6681 - Prédio 30 - Bloco 4, 90.619-900 - Porto Alegre - RS - Brasil. Phone: +55 51 33 20 36 11 - R.29, moraes@inf.pucrs.br
pp. 115-120

Single Event Transients in Combinatorial Circuits (PDF)

Gilson I Wirth , UERGS, 92500 Guaíba - RS, Brazil. +55 51 491-4042, gilson-wirth@uergs.edu.br
Michele G Vieira , UERGS, 92500 Guaíba - RS, Brazil. +55 51 491-4042. michele-vieira@uergs.edu.br
Egas Henes Neto , UERGS, 92500 Guaíba - RS, Brazil. +55 51 4914042, egas-henes@uergs.edu.br
F G L Kastensmidt , UFRGS, 91530 Porto Alegre - RS, Brazil. +55 51 3316-6816, fglima@inf.ufrgs.br
pp. 121-126

Design and Power Optimization of CMOS RF Blocks Operating in the Moderate Inversion Region (PDF)

Leonardo Barboni , Instituto de Ingeniería Eléctrica, Universidad de la República, Montevideo, Uruguay. Ibarboni@fing.edu.uy
Rafaella Fiorelli , Instituto de Ingeniería Eléctrica, Universidad de la República, Montevideo, Uruguay. fiorelli@fing.edu.uy
Fernando Silveira , Instituto de Ingeniería Eléctrica, Universidad de la República, Montevideo, Uruguay. silveira@fing.edu.uy
pp. 127-132

Dual-standard BiCMOS LNA for DCS1800/W-CDMA Applications (PDF)

C. P. Moreira , IXL Laboratory - UMR CNRS 5818 - ENSEIRB - University of Bordeaux - France. moreira@ixl.fr
E. Kerherve , Member, IEEE, IXL Laboratory - UMR CNRS 5818 - ENSEIRB - University of Bordeaux - France
P. Jarry , Senior Member, IEEE, IXL Laboratory - UMR CNRS 5818 - ENSEIRB - University of Bordeaux - France
D. Belot , STMicroelectronics - Crolles - France
pp. 133-137

Design of a Fully-integrated BiCMOS/FBAR Reconfigurable RF Receiver Front-End (PDF)

C. P. Moreira , IXL Laboratory - UMR CNRS 5818 - ENSEIRB - University of Bordeaux - France. moreira@ixl.fr
A. A. Shirakawa , IXL Laboratory - UMR CNRS 5818 - ENSEIRB - University of Bordeaux - France
E. Kerherve , IXL Laboratory - UMR CNRS 5818 - ENSEIRB - University of Bordeaux - France
J. M. Pham , IXL Laboratory - UMR CNRS 5818 - ENSEIRB - University of Bordeaux - France
P. Jarry , IXL Laboratory - UMR CNRS 5818 - ENSEIRB - University of Bordeaux - France
D. Belot , STMicroelectronics - Crolles - France
P. Ancey , STMicroelectronics - Crolles - France
pp. 138-143

A 3.5 mW Programmable High Speed Frequency Divider for a 2.4 GHz CMOS Frequency Synthesizer (PDF)

Angel M. Gomez Arguello , Escola Politécnica, Universidade de São Paulo, Av. Prof. Luciano Gualberto, 158 Trav. 3 CEP: 05508-900, São Paulo - SP - Brasil. (55)(11) 3091 5663, angel.arguello@freescale.com
S. Joao Navarro , Escola Politécnica, Universidade de São Paulo, Av. Prof. Luciano Gualberto, 158 Trav. 3 CEP: 05508-900, São Paulo - SP - Brasil. (55)(11) 3091 5663, navarro@lsi.usp.br
Wilhelmus Van Noije , Escola Politécnica, Universidade de São Paulo, Av. Prof. Luciano Gualberto, 158 Trav. 3 CEP: 05508-900, São Paulo - SP - Brasil. (55)(11) 3091 5668, noije@lsi.usp.br
pp. 144-148

Phase Noise Performances of a Cross-Coupled CMOS VCO with Resistor Tail Biasing (PDF)

Sergio Gagliolo , IEEE Student Member, Biophysical and Electronic Engineering Department - DIBE, University of Genoa, Via Opera Pia 11a 1-16145, Genoa, Italy. tel.: +39 010 353 2788, fax.: +39 010 353 2777, gagliolo@dibe.unige.it
Giacomo Pruzzo , Affiliated Researcher, Biophysical and Electronic Engineering Department - DIBE, University of Genoa, Via Opera Pia 11a 1-16145, Genoa, Italy. tel.: +39 010 353 2788, fax.: +39 010 353 2777, pruzzo@dibe.unige.it
Daniele D. Caviglia , IEEE Member, Full Professor, Biophysical and Electronic Engineering Department - DIBE, University of Genoa, Via Opera Pia 11a 1-16145, Genoa, Italy. tel.: +39 010 353 2788, fax.: +39 010 353 2777, caviglia@dibe.unige.it
pp. 149-153

Total Leakage Power Optimization with Improved Mixed Gates (PDF)

Frank Sill , College of CSEE, University of Rostock, Germany
Frank Grassert , College of CSEE, University of Rostock, Germany
Dirk Timmermann , College of CSEE, University of Rostock, Germany
pp. 154-159

Number Conversions between RNS and Mixed-Radix Number System Based on Modulo (2p - 1) Signed-Digit Arithmetic (PDF)

Shugang Wei , Department of Computer Scicence, Gunma University, 1-5-1, Tenjin-cho, Kiryu, Gunma, Japan. wei@ja4.cs.gunma-u.ac.jp
pp. 160-165

An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder Cells (PDF)

Mariano Aguirre , Department of Electronics INAOE-Mexico, P.O. Box 51 and 216, 72000, Puebla, Mexico, Phone/Fax: +52 (222) 247 05 17, maguirre@inaoep.mx
Monico Linares , Department of Electronics INAOE-Mexico, P.O. Box 51 and 216, 72000, Puebla, Mexico, Phone/Fax: +52 (222) 247 05 17, mlinares@inaoep.mx
pp. 166-171

Design of a Radix-2m Hybrid Array Multiplier Using Carry Save Adder (PDF)

M. Fonseca , Electrical Engineering Department, Universidade Católica de Pelotas, Pelotas, Brazil 412 - 96010-000. mrf@ucpel.tche.br
E. da Costa , Electrical Engineering Department, Universidade Católica de Pelotas, Pelotas, Brazil 412 - 96010-000. ecosta@ucpel.tche.br
S. Bampi , Microelectronics Group, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil 15064 - 91591-970. bampi@inf.ufrgs.br
J. Monteiro , Algos Group, IST/INESC-ID, Lisbon, Portugal 1000-029. jcm@inesc-id.pt
pp. 172-177

Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC (PDF)

Aline Mello , Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Predio 30 / Bloco C -90619-900 - Porto Alegre - RS - BRASIL. alinev@inf.pucrs.br
Leonel Tedesco , Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Predio 30 / Bloco C -90619-900 - Porto Alegre - RS - BRASIL. Itedesco@inf.pucrs.br
Ney Calazans , Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Predio 30 / Bloco C -90619-900 - Porto Alegre - RS - BRASIL. calazans@inf.pucrs.br
Fernando Moraes , Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Predio 30 / Bloco C -90619-900 - Porto Alegre - RS - BRASIL. moraes@inf.pucrs.br
pp. 178-183

Traffic Generation and Performance Evaluation for Mesh-based NoCs (PDF)

Leonel Tedesco , Pontificia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Prédio 30 / Bloco 4 - 90619-900 - Porto Alegre - RS - BRASIL. Itedesco@inf.pucrs.br
Aline Mello , Pontificia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Prédio 30 / Bloco 4 - 90619-900 - Porto Alegre - RS - BRASIL. alinev@inf.pucrs.br
Diego Garibotti , Pontificia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Prédio 30 / Bloco 4 - 90619-900 - Porto Alegre - RS - BRASIL. dgaribotti@inf.pucrs.br
Ney Calazans , Pontificia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Prédio 30 / Bloco 4 - 90619-900 - Porto Alegre - RS - BRASIL. calazans@inf.pucrs.br
Fernando Moraes , Pontificia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Av. Ipiranga, 6681 - Prédio 30 / Bloco 4 - 90619-900 - Porto Alegre - RS - BRASIL. moraes@inf.pucrs.br
pp. 184-189

Design Space Exploration Comparing Homogeneous and Heterogeneous Network-on-Chip Architectures (PDF)

Marcio Kreutz , Universidade Federal do Rio Grande do Sul - UFRGS/PPGC, Av. Bento Gonçalves, 9500. Prédio 43412 / Bloco IV - CEP: 91501-970 - Porto Alegre - RS - BRAZIL. kreutz@inf.ufrgs.br
Cesar A. Marcon , Universidade Federal do Rio Grande do Sul - UFRGS/PPGC, Av. Bento Gonçalves, 9500. Prédio 43412 / Bloco IV - CEP: 91501-970 - Porto Alegre - RS - BRAZIL. marcon@inf.ufrgs.br
Luigi Carro , Universidade Federal do Rio Grande do Sul - UFRGS/PPGC, Av. Bento Gonçalves, 9500. Prédio 43412 / Bloco IV - CEP: 91501-970 - Porto Alegre - RS - BRAZIL. carro@eletro.ufrgs.br
Flavio Wagner , Universidade Federal do Rio Grande do Sul - UFRGS/PPGC, Av. Bento Gonçalves, 9500. Prédio 43412 / Bloco IV - CEP: 91501-970 - Porto Alegre - RS - BRAZIL. flavio@inf.ufrgs.br
Altamiro A. Susin , Universidade Federal do Rio Grande do Sul - UFRGS/PPGC, Av. Bento Gonçalves, 9500. Prédio 43412 / Bloco IV - CEP: 91501-970 - Porto Alegre - RS - BRAZIL. susin@eletro.ufrgs.br
pp. 190-195

Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy Estimation (PDF)

Jose Carlos S. Palma , Universidade Federal do Rio, Grande do Sul - UFRGS/PPGC, Av. Bento Gongalves, 9500 - Prédio 43412 / Bloco IV, CEP: 91 501-970 - Porto Alegre - RS - BRAZIL. jcspalma@inf.ufrgs.br
Cesar Augusto M. Marcon , Universidade Federal do Rio, Grande do Sul - UFRGS/PPGC, Av. Bento Gongalves, 9500 - Prédio 43412 / Bloco IV, CEP: 91 501-970 - Porto Alegre - RS - BRAZIL. marcon@inf.ufrgs.br
Fernando G. Moraes , Pontificia Universidade Católica do, Rio Grande do Sul - FACIN, Av. Ipiranga, 6681 - Prédio 30 / Bloco 4, 90619-900 - Porto Alegre - RS - BRAZIL. moraes@inf.pucrs.br
Ney L. V. Calazans , Pontificia Universidade Católica do, Rio Grande do Sul - FACIN, Av. Ipiranga, 6681 - Prédio 30 / Bloco 4, 90619-900 - Porto Alegre - RS - BRAZIL. calazans@inf.pucrs.br
Ricardo A. L. Reis , Universidade Federal do Rio, Grande do Sul - UFRGS/PPGC, Av. Bento Gonçalves, 9500 - Prédio, 43412 / Bloco IV, CEP: 91501-970 - Porto Alegre - RS - BRAZIL. reis@inf.ufrgs.br
Altamiro A. Susin , Universidade Federal do Rio, Grande do Sul - UFRGS/PPGC, Av. Bento Gonçalves, 9500 - Prédio, 43412 / Bloco IV, CEP: 91501-970 - Porto Alegre - RS - BRAZIL. susin@eletro.ufrgs.br
pp. 196-201

Ultra-low Power CMOS Cells for Temperature Sensors (PDF)

Conrado Rossi , Instituto de Ing. Eléctrica, Facultad de Ingeniería, Universidad de la República, Montevideo, Uruguay. cra@fing.edu.uy
Pablo Aguirre , Instituto de Ing. Eléctrica, Facultad de Ingeniería, Universidad de la República, Montevideo, Uruguay. paguirre@fing.edu.uy
pp. 202-206

New Low-Voltage Electrically Tunable Triode-MOSFET Transconductor and its Application to Low-Frequency Gm-C Filtering (PDF)

Carlos Dualibe , Laboratorio de Microelectrónica, Universidad Católica de Córdoba, Camino a Alta Gracia KM 10 y 1/2, 5017-Córdoba-Argentina. TE: +54 351 4938089, dualibe@uccor.edu.ar
Pablo Petrashin , Laboratorio de Microelectrónica, Universidad Católica de Córdoba, Camino a Alta Gracia KM 10 y 1/2, 5017-Córdoba-Argentina. TE: +54 351 4938089, petra@uccor.edu.ar
Luis Toledo , Laboratorio de Microelectrónica, Universidad Católica de Córdoba, Camino a Alta Gracia KM 10 y 1/2, 5017-Córdoba-Argentina. TE: +54 351 4938089, toledo@uccor.edu.ar
Walter Lancioni , Laboratorio de Microelectrónica, Universidad Católica de Córdoba, Camino a Alta Gracia KM 10 y 1/2, 5017-Córdoba-Argentina. TE: +54 351 4938089, lancioni@uccor.edu.ar
pp. 207-212

An Efficient Chopper Amplifier, Using a Switched Gm-C Filter Technique (PDF)

Alfredo Arnaud , DIE Universidad Católica, 8 de Octubre 2738, Montevideo - Uruguay. +598-2 4872717 - ext.407, email: aarnaud@ucu.edu.uy
pp. 213-218

Minimization of Parasitic Effects on the Design of an Accurate 2-MHz RC Oscillator for Low Voltage and Low Power Applications (PDF)

Jung Hyun Choi , Freescale Semiconductors of Brazil, Brazil Semiconductor Technology Center (BSTC) -Power Management Group (PM), Rodovia SP340 - Km 128,7-A - Bairro Tanquinho - 13820-000 - Jaguariúna - SP - Brazil. Phone/Fax: +55-19-38476369 / 38478203, jung.choi@freescale.com
pp. 219-223

Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes (PDF)

Antonio Pullini , DEIS, Università di Bologna, Bologna 40136, Italy. antonio.pullini@studio.unibo.it
Federico Angiolini , DEIS, Università di Bologna, Bologna 40136, Italy. fangiolini@deis.unibo.it
Davide Bertozzi , Università di Ferrara, Ferrara 44100, Italy. dbertozzi@ing.unife.it
Luca Benini , DEIS, Università di Bologna, Bologna 40136, Italy. lbenini@deis.unibo.it
pp. 224-229

Performance Aware On-Chip Communication Synthesis and Optimization for Shared Multi-Bus Based Architecture (PDF)

Sujan Pandey , Institute of Microelectronics Systems, Darmstadt University of Technology, Karlstr. 15, D-64283 Darmstadt, Germany. pandey@mes.tu-darmstadt.de
Manfred Glesner , Institute of Microelectronics Systems, Darmstadt University of Technology, Karlstr. 15, D-64283 Darmstadt, Germany. glesner@mes.tu-darmstadt.de
Max Muhlhauser , Telecooperation Group, Darmstadt University of Technology, Hochschulstr. 10, D-64283 Darmstadt, Germany. max@informatik.tu-darmstadt.de
pp. 230-235

Placement of Intermodule Connections on Partially Reconfigurable Devices (PDF)

Florian Dittmann , Heinz Nixdorf Institute, University Paderborn, Fuerstenallee 11, 33102 Paderborn, Germany. roichen@upb.de
Markus Heberling , Heinz Nixdorf Institute, University Paderborn, Fuerstenallee 11, 33102 Paderborn, Germany. markush@upb.de
pp. 236-241

Non-Linear Addressing Scheme for a Lookup-Based Transformation Function in a Reconfigurable Noise Generator (PDF)

Elvio Dutra , Darmstadt University of Technology, Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Karlstrasse 15, D-64283 Darmstadt Germany. (+55) 21 2123-6569, (+49) 6151 16-4535, (+49) 6151 16-5136, elvio.dutra@bigfoot.com
Leandro Indrusiak , Darmstadt University of Technology, Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Karlstrasse 15, D-64283 Darmstadt Germany. (+55) 21 2123-6569, (+49) 6151 16-4535, (+49) 6151 16-5136, Isi@mes.tu-darmstadt.de
Manfred Glesner , Darmstadt University of Technology, Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Karlstrasse 15, D-64283 Darmstadt Germany. (+55) 21 2123-6569, (+49) 6151 16-4535, (+49) 6151 16-5136, glesner@mes.tu-darmstadt.de
pp. 242-247

A Continuous-time Hierarchical Field Programmable Analogue Array for Rapid Prototyping and Hierarchical Approach to Analogue Systems Design (PDF)

David Varghese , School of Electronics and Computer Science, University of Southampton, UK S017 1 BJ. dvarghes@soton.ac.uk
J. N. Ross , School of Electronics and Computer Science, University of Southampton, UK S017 1 BJ. jnr@ecs.soton.ac.uk
pp. 248-253

Author index (PDF)

pp. 254
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