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Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (2004)
Porto de Galinhas, Pernambuco, Brazil
Sept. 11, 2004 to Sept. 11, 2004
ISBN: 1-58113-947-0
TABLE OF CONTENTS

Copyright page (PDF)

pp. ii

Table of contents (PDF)

pp. iv-vii

Reviewers (PDF)

pp. x

RTL power estimation and optimization (PDF)

E. Macii , Dipt. di Autom. e Inf., Politecnico di Torino, Italy
pp. 1

Statistical analysis and design: from picoseconds to probabilities (PDF)

C. Visweswariah , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 2

Architecture and CAD for FPGAs (PDF)

M. Hutton , Altera Corp., San Jose, CA, USA
pp. 3

Test and design-for-test of mixed-signal integrated circuits (PDF)

J.L. Huertas , Instituto de Microelectron. de Sevilla, CNM, Sevilla, Spain
pp. 4

Will the ASIC survive? (PDF)

R. Camposano , Synopsys Inc., Mountain View, CA, USA
pp. 5

Leakage power optimization in standard-cell designs (PDF)

E. Macii , Dipt. di Autom. e Inf., Politecnico di Torino, Italy
pp. 7

Advances and trends in FPGA design (PDF)

M. Hutton , Altera Corp., San Jose, CA, USA
pp. 8

Verification and test challenges in SoC designs (PDF)

C.A.M. Duenas , Freescale Semicond. Inc., Jaguariuna, Brazil
pp. 9

PADReH - a framework for the design and implementation of dynamically and partially reconfigurable systems (PDF)

E. Carvalho , Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil
N. Calazans , Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil
E. Briao , Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil
F. Moraes , Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil
pp. 10-15

A partial reconfigurable architecture for controllers based on Petri nets (PDF)

P.S.B. Nascimento , Inf. Center, Fed. Univ. of Pernambuco, Recife, Brazil
P.R.M. Maciel , Inf. Center, Fed. Univ. of Pernambuco, Recife, Brazil
M.E. Lima , Inf. Center, Fed. Univ. of Pernambuco, Recife, Brazil
R.E. Sant'ana , Inf. Center, Fed. Univ. of Pernambuco, Recife, Brazil
A.G.S. Filho , Inf. Center, Fed. Univ. of Pernambuco, Recife, Brazil
pp. 16-21

Task scheduling for heterogeneous reconfigurable computers (PDF)

A. Ahmadinia , Dept. of Comput. Sci., Erlangen-Nurnberg Univ., Erlangen, Germany
C. Bobda , Dept. of Comput. Sci., Erlangen-Nurnberg Univ., Erlangen, Germany
D. Koch , Dept. of Comput. Sci., Erlangen-Nurnberg Univ., Erlangen, Germany
M. Majer , Dept. of Comput. Sci., Erlangen-Nurnberg Univ., Erlangen, Germany
J. Teich , Dept. of Comput. Sci., Erlangen-Nurnberg Univ., Erlangen, Germany
pp. 22-27

Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration (PDF)

M. Huebner , Karlsruhe Univ., Germany
T. Becker , Karlsruhe Univ., Germany
J. Becker , Karlsruhe Univ., Germany
pp. 28-32

Characterization of MOS transistor current mismatch (PDF)

H. Klimach , Univ. Fed. de Santa Catarina, Florianopolis, Brazil
pp. 33-38

A 0.8 /spl mu/m CMOS switched-capacitor video filter (PDF)

A. Petraglia , COPPE, Univ. Fed. do Rio de Janeiro, Brazil
pp. 39-43

A 1.8 V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability (PDF)

A.L.V. Boas , Motorola - Brazil Semicond. Technol. Center, Sao Paulo, Brazil
J.B.D. Soldera , Motorola - Brazil Semicond. Technol. Center, Sao Paulo, Brazil
A. Olmos , Motorola - Brazil Semicond. Technol. Center, Sao Paulo, Brazil
pp. 44-48

Modeling and designing high performance analog reconfigurable circuits (PDF)

E.E. Fabris , Inf. Inst., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 49-54

TheoSim: combining symbolic simulation and theorem proving for hardware verification (PDF)

G.A. Sammane , TIMA Lab., VDS Group, Grenoble, France
J. Schmaltz , TIMA Lab., VDS Group, Grenoble, France
D. Toma , TIMA Lab., VDS Group, Grenoble, France
P. Ostier , TIMA Lab., VDS Group, Grenoble, France
D. Borrione , TIMA Lab., VDS Group, Grenoble, France
pp. 60-65

Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF (PDF)

J.V. do Vale Neto , Dept. de Sistemas Eletronicos, Sao Paulo Univ., Brazil
pp. 76-81

Dual-mode RF receiver front-end using a 0.25-/spl mu/m 60-GHz f/sub T/ SiGe:C BiCMOS7RF technology (PDF)

C.P. Moreira , IXL Lab., Bordeaux Univ., Bordeaux, France
E. Kerherve , IXL Lab., Bordeaux Univ., Bordeaux, France
P. Jarry , IXL Lab., Bordeaux Univ., Bordeaux, France
A.A. Shirakawa , IXL Lab., Bordeaux Univ., Bordeaux, France
pp. 88-93

A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 /spl mu/m CMOS technology (PDF)

F.P.H. de Miranda , Escola Politecnica, Sao Paulo Univ., Brazil
S.J. Navarro , Escola Politecnica, Sao Paulo Univ., Brazil
pp. 94-99

ATPG for fault diagnosis on analog electrical networks using evolutionary techniques (PDF)

C.E.F. Savioli , Brazilian Navy Electron. Center, Rio de Janeiro, Brazil
C.E.C. Szendrodi , Brazilian Navy Electron. Center, Rio de Janeiro, Brazil
pp. 100-104

Improving mixed-single SOC testing: a power-aware reuse-based approach with analog BIST (PDF)

A. Andrade , Electr. Eng. Dept., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 105-110

Reducing test time with processor reuse in network-on-chip based systems (PDF)

A.M. Amory , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
E. Cota , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 111-116

Accurate capture of timing parameters in inductively-coupled on-chip interconnects (PDF)

T. Murugan , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
C. Schlachta , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Petrov , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
L. Indrusiak , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 117-122

Issues in parallelizing multigrid-based substrate model extraction and analysis (PDF)

J.M.S. Silva , Tech. Univ. of Lisbon, Portugal
L.M. Silveria , Tech. Univ. of Lisbon, Portugal
pp. 123-128

An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs (PDF)

G. Trucco , Dept. of Inf. Technol., Univ. of Milano, Crema, Italy
G. Boselli , Dept. of Inf. Technol., Univ. of Milano, Crema, Italy
V. Liberali , Dept. of Inf. Technol., Univ. of Milano, Crema, Italy
pp. 129-134

Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures (PDF)

A. Thomas , Inst. fur Tech. der Inf., Univ. Karlsruhe, Germany
T. Zander , Inst. fur Tech. der Inf., Univ. Karlsruhe, Germany
J. Becker , Inst. fur Tech. der Inf., Univ. Karlsruhe, Germany
pp. 141-146

An ultra-low-power self-biased current reference (PDF)

E.M. Camacho-Galeano , Integrated Circuits Lab., Univ. of Santa Catarina, Florianopolis, Brazil
pp. 147-150

A fully integrated physical activity sensing circuit for implantable pacemakers (PDF)

A. Arnaud , GME-IIE, Univ. de la Republica, Montevideo, Uruguay
pp. 151-156

A VLIW low power Java processor for embedded applications (PDF)

A.C.S. Beck , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 157-162

A formal software synthesis approach for embedded hard real-time systems (PDF)

R. Barreto , Centro de Inf., Univ. Fed. de Pernambuco, Recife, Brazil
M. Neves , Centro de Inf., Univ. Fed. de Pernambuco, Recife, Brazil
pp. 163-168

Accurate software performance estimation using domain classification and neural networks (PDF)

M.S. Oyamada , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
F. Zschornack , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
F.R. Wanger , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 175-180

Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic (PDF)

M.C.B. Osorio , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
C.A. Sampaio , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
A.I. Reis , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
R.P. Ribas , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 181-185

A programmable cellular neural network circuit (PDF)

M. Leong , INESC, Instituto Superior Tecnico, Lisbon, Portugal
P. Vasconcelos , INESC, Instituto Superior Tecnico, Lisbon, Portugal
J.R. Fernandes , INESC, Instituto Superior Tecnico, Lisbon, Portugal
L. Sousa , INESC, Instituto Superior Tecnico, Lisbon, Portugal
pp. 186-191

A multi-standard channel-decoder for base-station applications (PDF)

T. Vogt , Kaiserslautern Univ., Germany
N. Wehn , Kaiserslautern Univ., Germany
pp. 192-197

FPGA implementation of parallel turbo-decoders (PDF)

M.J. Thul , Kaiserslautern Univ., Germany
N. Wehn , Kaiserslautern Univ., Germany
pp. 198-203

A switch architecture and signal synchronization for GALS system-on-chips (PDF)

P. Zipf , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
H. Hinkelmann , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
A. Ashraf , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 210-215

When reconfigurable architecture meets network-on-chip (PDF)

R. Soares , DIMAP, Univ. Fed. do Rio Grande do Norte, Natal, Brazil
pp. 216-221

On the dynamic behavior of a novel digital-only sigma-delta A/D converter (PDF)

M. Jacomet , Interdisciplinary Inst. of Integrated Syst., Univ. of Appl. Sci. Bern, Biel-Bienne, Switzerland
J. Goette , Interdisciplinary Inst. of Integrated Syst., Univ. of Appl. Sci. Bern, Biel-Bienne, Switzerland
V. Zbinden , Interdisciplinary Inst. of Integrated Syst., Univ. of Appl. Sci. Bern, Biel-Bienne, Switzerland
C. Narvaez , Interdisciplinary Inst. of Integrated Syst., Univ. of Appl. Sci. Bern, Biel-Bienne, Switzerland
pp. 222-227

A low power 13-Gb/s 2/sup 7/-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS (PDF)

H.-D. Wohlmuth , Corp. Res., Infineon Technol. AG, Munich, Germany
D. Kehrer , Corp. Res., Infineon Technol. AG, Munich, Germany
pp. 233-236

An improved synthesis method for low power hardwired FIR filters (PDF)

V.S. Rosa , Inf. Inst., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 237-241

Advanced technology mapping for standard-cell generators (PDF)

V. Correia , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
A. Reis , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 254-259

Non-Manhattan maze routing (PDF)

M.R. Stan , ECE Dept., Virginia Univ., Charlottesville, VA, USA
F. Hamzaoglu , ECE Dept., Virginia Univ., Charlottesville, VA, USA
D. Garrett , ECE Dept., Virginia Univ., Charlottesville, VA, USA
pp. 260-265

[Breaker page] (PDF)

pp. 266

Body-bias compensation technique for subthreshold CMOS static logic gates (PDF)

L.A.P. Melek , Univ. Fed. de Santa Catarina, Florianopolis, Brazil
M.C. Schneider , Univ. Fed. de Santa Catarina, Florianopolis, Brazil
C. Galup-Montoro , Univ. Fed. de Santa Catarina, Florianopolis, Brazil
pp. 267-272

Low power gate-level design with mixed-V/sub th/ (MVT) techniques (PDF)

F. Sill , Fac. of Comput. Sci. and Electr. Eng., Rostock Univ., Germany
F. Grassert , Fac. of Comput. Sci. and Electr. Eng., Rostock Univ., Germany
D. Timmermann , Fac. of Comput. Sci. and Electr. Eng., Rostock Univ., Germany
pp. 278-282

Author index (PDF)

pp. 283-284

[Breaker page] (PDF)

pp. 285

[Back cover] (PDF)

pp. 286
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