The Community for Technology Leaders
Integrated Circuit Design and System Design, Symposium on (2003)
S?o Paulo, Brazil
Sept. 8, 2003 to Sept. 11, 2003
ISBN: 0-7695-2009-X
TABLE OF CONTENTS
Introduction

Foreword (PDF)

pp. x

Reviewers (PDF)

pp. xiii
Tutorials

System-Level Design for FPGAs (PDF)

Patrick Lysaght , Xilinx Research Labs
pp. 4
Session 1A: Advanced Amplifier Design

A Methodology for CMOS Low Noise Ampli.er Design (Abstract)

João Navarro Soares , São Paulo University
Wilhelmus Van Noije , São Paulo University
Elkim Roa , São Paulo University
pp. 14

Design of a Reusable Rail-to-Rail Operational Amplifier (Abstract)

Pablo Aguirre , Universidad de la República
Fernando Silveira , Universidad de la República
pp. 20

Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs (Abstract)

D. Flandre , Universidade de S?o Paulo
M. A. Pavanello , Universidade de S?o Paulo
S. P. Gimenez , Universidade de S?o Paulo
J. A. Martino , Universidade de S?o Paulo
S. Adriaensen , Universidade de S?o Paulo
pp. 26
Session 1B: Logic Synthesis Techniques

Boolean Technology Mapping Based on Logic Decomposition (Abstract)

Andrei Y. Selchenko , DariaSoft, Inc.
Maurizio Damiani , Sierra Design Automation
pp. 35

Retiming Finite State Machines to Control Hardened Data-Paths (Abstract)

Ivan Aug? , Universit? Pierre et Marie Curie
Fran?ois Donnet , Universit? Pierre et Marie Curie
Fr?d?ric P?trot , Universit? Pierre et Marie Curie
pp. 41

Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits (Abstract)

Luca P. Carloni , University of California at Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
pp. 47

Simplification of Toffoli Networks via Templates (Abstract)

D. Michael Miller , University of Victoria
Dmitri Maslov , University of New Brunswick
GerhardW. Dueck , University of New Brunswick
pp. 53
Session 2: Invited Paper
Session 3A: Digital Design Techniques

Novel Design Methodology for High-Performance XOR-XNOR Circuit Design (Abstract)

Sumeer Goel , University of Louisiana at Lafayette
Mohamed A. Elgamel , University of Louisiana at Lafayette
Magdy A. Bayoumi , University of Louisiana at Lafayette
pp. 71
Session 3B: High-Level and Co-Design Approaches

Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures (Abstract)

Achim Rettberg , University of Paderborn
Thomas Lehmann , University of Paderborn
Florian Dittmann , University of Paderborn
Mauro Zanella , University of Paderborn
pp. 79
Session 4A: Mapping Applications onto FPGAs

ME64 — A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA (Abstract)

Marcel Bergerman , Genius Institute of Technology
Sergio Bampi , Federal University of Rio Grande do Sul
Diogo Zandonai , Federal University of Rio Grande do Sul and Genius Institute of Technology
pp. 93

Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm (Abstract)

Michelle Matos Horta , Universidade Federal de Pernambuco
Abel Guilhermino da S. Filho , Universidade Federal de Pernambuco
Manoel Eusebio de Lima , Universidade Federal de Pernambuco
Jorge Cerqueira , Universidade Federal de Pernambuco
Haglay Alice , Universidade Federal de Pernambuco
Alejandro C. Frery , Universidade Federal de Pernambuco
Juliana A. Loureiro , Universidade Federal de Pernambuco
Maria das Gra?as S. Oliveira , Universidade Federal de Pernambuco
Cristiano Co?lho de Ara? , Universidade Federal de Pernambuco
pp. 99

Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs (Abstract)

Felipe Haffner , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
Sandro Ferreira , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
Fernando Moraes , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
Lu?s Fernando Pereira , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
pp. 105

FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. Stochastic (Abstract)

Luiza de Macedo Mourelle , State University of Rio de Janeiro
Nadia Nedjah , State University of Rio de Janeiro
pp. 111
Session 4B: IP Integration Techniques

An XML Format Based Integration Infrastructure for IP Based Design (Abstract)

Frank Kelso , University of Minnesota
Wolfram Hardt , University of Paderborn
Markus Visarius , University of Paderborn
Johannes Lessmann , University of Paderborn
Wolfgang Thronicke , Siemens Business Services
pp. 119

Tangram — Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation Environment (Abstract)

Uilian R. F. Souza , Universidade Federal do Rio Grande do Sul
Br?ulio A. de Mello , Universidade Federal do Rio Grande do Sul and Universidade Regional Integrada do Alto Uruguai
Fl?vio R. Wagner , Universidade Federal do Rio Grande do Sul
Josu? K. Sperb , Universidade Federal do Rio Grande do Sul
pp. 125

A Fast IP-Core Integration Methodology for SoC Design (Abstract)

Paulo Romero Maciel , Federal University of Pernambuco
Manoel Eus?bio de Lima , Federal University of Pernambuco
Juliana Moura , Federal University of Pernambuco
Julio A. de Oliveira Filho , Federal University of Pernambuco
Bruno Celso , Federal University of Pernambuco
pp. 131

A Universal High-Performance Analog Interface for Signal Processing SOCs (Abstract)

Sergio Bampi , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
Eric E. Fabris , Universidade Federal do Rio Grande do Sul
pp. 137
Session 5: Invited Paper
Session 6A: Asynchronous Design Techniques

Automatic Generation of 1-of-M QDI Asynchronous Adders (Abstract)

Jo? Fragoso , TIMA Laboratory
Gilles Sicard , TIMA Laboratory
Marc Renaudin , TIMA Laboratory
pp. 149

Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits (Abstract)

António Ferrari , Universidade de Aveiro
Artur Pereira , Universidade de Aveiro
António Rui Borges , Universidade de Aveiro
pp. 155
Session 6B: Networks-on-Chip

Algorithms and Tools for Network on Chip Based System Design (Abstract)

Tang Lei , J?nk?ping University
Shashi Kumar , J?nk?ping University
pp. 163

SoCIN: A Parametric and Scalable Network-on-Chip (Abstract)

Altamiro Amadeu Susin , Universidade Federal do Rio Grande do Sul
Cesar Albenes Zeferino , Universidade Federal do Rio Grande do Sul and Universidade do Vale do Itaja?
pp. 169
Session 7A: Application Specific RF and Analog Design

A Low Ripple Fully Integrated Charge Pump Regulator (Abstract)

A. Vilas Boas , Motorola — Brazil Semiconductor Technology Center
A. Olmos , Motorola — Brazil Semiconductor Technology Center
J. Soldera , Motorola — Brazil Semiconductor Technology Center
pp. 177

A Temperature Compensated Fully Trimmable On-Chip IC Oscillator (Abstract)

A. Olmos , Motorola — Brazil Semiconductor Technology Center
pp. 181

Bias Dependence of Noise Correlation in MAGFETs (Abstract)

Fernando C. Castaldo , State University of Londrina
Carlos Alberto dos Reis , State University of Campinas
Jo?o Paulo C. Cajueiro , State University of Campinas
pp. 187

A Charge Correction Cell for FGMOS-Based Circuits (Abstract)

Esther O. Rodr?guez-Villegas , Universidad de Sevilla
Alberto Y?fera , Universidad de Sevilla
Adoraci? Rueda , Universidad de Sevilla
pp. 191
Session 7B: Applications of Formal Methods to Design

Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic (Abstract)

Mauricio Ayala-Rinc? , Universidade de Bras?lia
Ricardo P. Jacobi , Universidade de Bras?lia
Rodrigo B. Nogueira , Universidade de Bras?lia
Carlos H. Llanos , Universidade de Bras?lia
Reiner W. Hartenstein , Universit?t Kaiserlautern
pp. 205

Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification (Abstract)

K. Schneider , University of Kaiserslautern
G. Logothetis , University of Karlsruhe
C. Metzler , University of Karlsruhe
pp. 211

A Consumer Report on BDD Packages (Abstract)

Geert Janssen , IBM T.J. Watson Research Center
pp. 217
Session 8A: Novel Architectures

A New Hybrid Parallel/Reconfigurable Architecture:The X4CP32 (Abstract)

Arnold Azevedo , Universidade Federal do Rio Grande do Norte
Rodrigo Soares , Universidade Federal do Rio Grande do Norte
Ivan Saraiva Silva , Universidade Federal do Rio Grande do Norte
pp. 225

Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture (Abstract)

Ulrich Dierkes , University of Paderborn
Carsten Rustemeier , University of Paderborn
Mauro Zanella , University of Paderborn
Achim Rettberg , University of Paderborn
Thomas Lehmann , University of Paderborn
pp. 231

Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration (Abstract)

Maik Scheer , Universitaet Karlsruhe
Juergen Becker , Universitaet Karlsruhe
Alexander Thomas , Universitaet Karlsruhe
pp. 237
Session 8B: Noise Analysis and Layout

On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction (Abstract)

Howard H. Chen , IBM Corporation
Gricel Co , IBM Corporation
J. Scott Neely , IBM Corporation
Michael F. Wang , IBM Corporation
pp. 251

Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction (Abstract)

Magdy A. Bayoumi , University of Louisiana at Lafayette
Mohamed A. Elgamel , University of Louisiana at Lafayette
pp. 256

A New Continuous Switching Window Computation with Crosstalk Noise (Abstract)

Omar Hafiz , University of Arizona at Tucson
Pinhong Chen , Cadence Corperation
Janet Meiling Wang , University of Arizona at Tucson
pp. 261

Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations (Abstract)

Ricardo Augusto da Luz Reis , Universidade Federal do Rio Grande do Sul
Renato Fernandes Hentschke , Universidade Federal do Rio Grande do Sul
pp. 267
Session 9: Invited Paper

Future Design Tools for Platform FPGAs (Abstract)

Patrick Lysaght , Xilinx Research Labs
pp. 275
Session 10A: Issues in Reconfigurable Architectures

Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations (Abstract)

Juergen Becker , Universitaet Karlsruhe
Michael Ullmann , Universitaet Karlsruhe
Michael Huebner , Universitaet Karlsruhe
pp. 283
Session 10B: Timing Analysis and Layout

Improving Critical Path Identification in Functional Timing Analysis (Abstract)

Daniel Ferr? , Universidade Federal do Rio Grande do Sul
Ricardo Reis , Universidade Federal do Rio Grande do Sul
Jos? Lu? G?ntzel , Universidade Federal de Pelotas
Gustavo Wilke , Universidade Federal do Rio Grande do Sul
pp. 297

A Transistor Sizing Method Applied to an Automatic Layout Generation Tool (Abstract)

Cristiano Lazzari , Universidade Federal do Rio Grande do Sul
José Luís Güntzel , Universidade Federal de Pelotas
Gustavo Wilke , Universidade Federal do Rio Grande do Sul
Ricardo Reis , Universidade Federal do Rio Grande do Sul
Cristiano Santos , Universidade Federal do Rio Grande do Sul
pp. 303
Session 11A: Innovative Approaches to RF and Analog Design Problems

Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35?m Technology (Abstract)

Eric Fabris , Federal University of Rio Grande do Sul
Sergio Bampi , Federal University of Rio Grande do Sul
Alessandro Girardi , Federal University of Rio Grande do Sul
Fernando Paix? Cortes , Federal University of Rio Grande do Sul
pp. 311

Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages (Abstract)

Antonio J. Gin? , Instituto de Microelect?nica de Sevilla
Eduardo J. Peral?as , Instituto de Microelect?nica de Sevilla
Adoraci? Rueda , Instituto de Microelect?nica de Sevilla
pp. 317

Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends (Abstract)

Fabien Mieyeville , Ecole Centrale de Lyon
Frédéric Gaffiot , Ecole Centrale de Lyon
Ian O?Connor , Ecole Centrale de Lyon
Faress Tissafi-Drissi , Ecole Centrale de Lyon
pp. 323

Testing RF Signal Paths Using Spectral Analysis and Subsampling (Abstract)

Marcelo Negreiros , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
Erik Schuler , Universidade Federal do Rio Grande do Sul
Altamiro A. Susin , Universidade Federal do Rio Grande do Sul
pp. 329
Session 11B: High-Level Validation and Modeling

Accurate Dependability Analysis of CAN-Based Networked Systems (Abstract)

M. Violante , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
J. P?rez , Universidad de la Rep?blica
pp. 337

ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware (Abstract)

Jürgen Teich , University of Erlangen-Nuremberg
Dirk Koch , University of Erlangen-Nuremberg
Christian Haubelt , University of Erlangen-Nuremberg
pp. 343

CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator (Abstract)

Fl?vio R. Wagner , Universidade Federal do Rio Grande do Sul
Antonio C. S. Beck Filho , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
Julio C. B. Mattos , Universidade Federal do Rio Grande do Sul
pp. 349

From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study (Abstract)

Edson Moreno , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
Vitor Rosa , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
Ney Calazans , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
Fernando Moraes , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
Fabiano Hessel , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
Everton Carara , Pontif?cia Universidade Cat?lica do Rio Grande do Sul
pp. 355
Author Index

Author Index (PDF)

pp. 361
106 ms
(Ver 3.1 (10032016))