The Community for Technology Leaders
Integrated Circuit Design and System Design, Symposium on (2000)
Manaus, Brazil
Sept. 18, 2000 to Sept. 24, 2000
ISBN: 0-7695-0843-X
TABLE OF CONTENTS

Foreword (PDF)

pp. x

Reviewers (PDF)

pp. xiii
Session 1-Design for Test

Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits (Abstract)

P. Faure , LIRMM-UM2, Montpellier, France
J. Figueras , LIRMM-UM2, Montpellier, France
Y. Zorian , LIRMM-UM2, Montpellier, France
J.M. Portal , LIRMM-UM2, Montpellier, France
M. Renovell , LIRMM-UM2, Montpellier, France
pp. 3

Solving the I/O Bandwidth Problem in System on a Chip Testing (Abstract)

M. Benabdenbi , LIP6 Lab., Paris, France
M. Marzouki , LIP6 Lab., Paris, France
W. Maroufi , LIP6 Lab., Paris, France
pp. 9

Testability Properties of Vertex Precedent BDDs (Abstract)

M. Lubaszewski , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
A. Reis , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
A. Prado , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 15

ATG-Based Timing Analysis of Circuits Containing Complex Gates (Abstract)

E. d'Avila , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
R. Reis , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
J.L. Guntzel , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
A.C. Medina Pinto , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 21
Session 2-Microarchitectures-Architecture

A Bit Scalable Architecture for Fuzzy Processors with Three Inputs and a Flexible Fuzzification Unit (Abstract)

R. d'Amore , Inst. Tecnologico de Aeronaut., Sao Jose dos Campos, Brazil
pp. 29

Partitioned Branch Condition Resolution Logic (Abstract)

V.G. Oklobdzija , Synopsys Module Compiler Group, Synopsys Inc., Mountain View, CA, USA
A. Farooqui , Synopsys Module Compiler Group, Synopsys Inc., Mountain View, CA, USA
K.W. Current , Synopsys Module Compiler Group, Synopsys Inc., Mountain View, CA, USA
pp. 35

Synthesis of High Performance Extended Burst Mode Asynchronous State Machines (Abstract)

W. Chiepa Cunha , Dept. de Eletron. Aplicada, Inst. Tecnologico de Aeronaut., Sao Paulo, Brazil
M. Strum , Dept. de Eletron. Aplicada, Inst. Tecnologico de Aeronaut., Sao Paulo, Brazil
Wang Jiang Chau , Dept. de Eletron. Aplicada, Inst. Tecnologico de Aeronaut., Sao Paulo, Brazil
D. Lopes de Oliveira , Dept. de Eletron. Aplicada, Inst. Tecnologico de Aeronaut., Sao Paulo, Brazil
pp. 41

Improved IDEA (Abstract)

F.M.G. Franca , Mil. Inst. of Eng., Rio de Janeiro, Brazil
S.L.C. Salomao , Mil. Inst. of Eng., Rio de Janeiro, Brazil
J.M.S. de Alcantara , Mil. Inst. of Eng., Rio de Janeiro, Brazil
V.C. Alves , Mil. Inst. of Eng., Rio de Janeiro, Brazil
pp. 47
Session 3-Logic Design

Revisiting Hamiltonian Decomposition of the Hypercube (Abstract)

S.W. Song , Inst. de Matematica e Estatistica, Sao Paulo Univ., Brazil
K. Okuda , Inst. de Matematica e Estatistica, Sao Paulo Univ., Brazil
pp. 55

An Input-Output Encoding Approach for Serial Decomposition (Abstract)

V. Muthukumar , GSCIT, Monash Univ., Clayton, Vic., Australia
H. Selvaraj , GSCIT, Monash Univ., Clayton, Vic., Australia
R. Bignall , GSCIT, Monash Univ., Clayton, Vic., Australia
pp. 61

Disjunctive Decomposition of Switching Functions Using Symmetry Information (Abstract)

M. Chrzanowska-Jeske , Portland State Univ., OR, USA
M. Jeske , Portland State Univ., OR, USA
Jing Xia , Portland State Univ., OR, USA
Wei Wang , Portland State Univ., OR, USA
pp. 69

Methods Based on Petri Net for Resource Sharing Estimation (Abstract)

F. Cruz Filho , Dept. de Engenharia Eletrica, Univ. Fed. de Pernambuco, Recife, Brazil
W. Rosenstiel , Dept. de Engenharia Eletrica, Univ. Fed. de Pernambuco, Recife, Brazil
P. Maciel , Dept. de Engenharia Eletrica, Univ. Fed. de Pernambuco, Recife, Brazil
E. Barros , Dept. de Engenharia Eletrica, Univ. Fed. de Pernambuco, Recife, Brazil
pp. 75
Session 4-Analog Design

Robust Implementation and Statistical Modeling of a VI-Converter (Abstract)

R. Schuffny , Dept. of Electr. Eng., Tech. Univ. Dresden, Germany
A. Graupner , Dept. of Electr. Eng., Tech. Univ. Dresden, Germany
pp. 83

Resizing Rules for the Reuse of MOS Analog Designs (Abstract)

C. Galup-Montoro , Fed.. Univ. of Santa Catarina, Brazil
M.C. Schneider , Fed.. Univ. of Santa Catarina, Brazil
pp. 89

Analysis and Design of a Family of Low-Power Class AB Operational Amplifiers (Abstract)

D. Flandre , Inst. de Ingegneria Electr., Univ. de la Republica, Montevideo, Uruguay
F. Silveira , Inst. de Ingegneria Electr., Univ. de la Republica, Montevideo, Uruguay
pp. 94

A Generator of Trapezoidal Association of Transistors (TAT): Improving Analog Circuits in a Pre-Diffused Transistor Array (Abstract)

A. Luiz Aita , Dept. of Electron. & Comput., Fed.. Univ. of Santa Maria, Brazil
Jung Hyun Choi , Dept. of Electron. & Comput., Fed.. Univ. of Santa Maria, Brazil
S. Bampi , Dept. of Electron. & Comput., Fed.. Univ. of Santa Maria, Brazil
pp. 99
Session 5-High Level Synthesis

Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP Algorithms (Abstract)

B. Mesman , Sect. of Design Autom., Eindhoven Univ. of Technol., Netherlands
K. van Eijk , Sect. of Design Autom., Eindhoven Univ. of Technol., Netherlands
C.A. Alba Pinto , Sect. of Design Autom., Eindhoven Univ. of Technol., Netherlands
J. Jess , Sect. of Design Autom., Eindhoven Univ. of Technol., Netherlands
pp. 107

Register Binding for Predicated Execution in DSP Applications (Abstract)

J.A.G. Jess , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
C.A.J. van Eijk , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
Q. Zhao , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
C.A. Alba Pinto , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
pp. 113

A Data Path Synthesis Method to Self-Testable Application Specific Integrated Circuit (ASIC) (Abstract)

J. Vieira do Vale Neto , Escola Politecnica, Sao Paulo Univ., Brazil
J. Perez R. Cost , Escola Politecnica, Sao Paulo Univ., Brazil
pp. 119

From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave Project (Abstract)

L. Soares Indrusiak , Dept. de Inf., Pontificia Univ. Catolica do Rio Grande do Sul, Brazil
R. Augusto da Luz Reis , Dept. de Inf., Pontificia Univ. Catolica do Rio Grande do Sul, Brazil
pp. 125
Session 6-Physical Design

WTROPIC: A WWW-Based Macro-Cell Generator (Abstract)

R. Reis , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
F. Moraes , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
J.L. Fragoso , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 133

Modular Exponentiation on Fine-Grained FPGA (Abstract)

E. Trichina , Inst. of Math., Acad. of Sci., Minsk, Byelorussia
A. Tiountchik , Inst. of Math., Acad. of Sci., Minsk, Byelorussia
pp. 139

Net by Net Routing with a New Path Search Algorithm (Abstract)

R. Reis , Inst. de Inf., Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
M. Johann , Inst. de Inf., Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
pp. 144

Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-Transistor (Abstract)

F.J. Tegude , Dept. of Microelectron., Dortmund Univ., Germany
W. Prost , Dept. of Microelectron., Dortmund Univ., Germany
G.I. Wirth , Dept. of Microelectron., Dortmund Univ., Germany
P. Velling , Dept. of Microelectron., Dortmund Univ., Germany
M. Agethen , Dept. of Microelectron., Dortmund Univ., Germany
P. Glosekotter , Dept. of Microelectron., Dortmund Univ., Germany
K.F. Goser , Dept. of Microelectron., Dortmund Univ., Germany
C. Pacha , Dept. of Microelectron., Dortmund Univ., Germany
U. Auer , Dept. of Microelectron., Dortmund Univ., Germany
pp. 150
Session 7-System Level Design

On the Choice of Models of Computation for Writing Executable Specifications of System Level Designs (Abstract)

I. Jeukens , Lab. de Microelectron., Sao Paulo Univ., Brazil
M. Strum , Lab. de Microelectron., Sao Paulo Univ., Brazil
pp. 159

Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs (Abstract)

V.M. Goulart Ferreira , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
H. Yasuura , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
pp. 165

Modeling an E1/TU12 Mapper for SDH Systems (Abstract)

W.A.M. Van Noije , Escola Politecnica, Sao Paulo Univ., Brazil
R. Silveira , Escola Politecnica, Sao Paulo Univ., Brazil
pp. 171

JPEG Decoding in an Electronic Voting Machine (Abstract)

R. Cantanhede , Dept. de Ciencia da Comput., Brasilia Univ., Brazil
J. Porfirio A. de Carvalh , Dept. de Ciencia da Comput., Brasilia Univ., Brazil
F. Trindade , Dept. de Ciencia da Comput., Brasilia Univ., Brazil
R. Pezzuol Jacobi , Dept. de Ciencia da Comput., Brasilia Univ., Brazil
pp. 177
Session 8-Industrial Applications/Applications of FPGAs

An FPGA Implementation of the ATM Layer (Abstract)

E.U.K. Melchier , Univ. Fed. da Paraiba, Joao Pessoa, Brazil
H. Soares da Silva , Univ. Fed. da Paraiba, Joao Pessoa, Brazil
J.A. Gomes de Lima , Univ. Fed. da Paraiba, Joao Pessoa, Brazil
pp. 185

Prototyping a Pager-Like Device Using FPGAs: Design of an Object Finder (Abstract)

W.A.M. Van Noije , Escola Politecnica, Sao Paulo Univ., Brazil
G.A. Cerezo Vasquez , Escola Politecnica, Sao Paulo Univ., Brazil
S.E. Barbin , Escola Politecnica, Sao Paulo Univ., Brazil
pp. 191

Jet Determination in Liquid Argon Calorimeters Using a Heavily Interconnected System of Field Programmable Gate Arrays (Abstract)

C. Kiesling , Werner Heisenberg Inst., Max-Planck-Inst. fur Phys., Munchen, Germany
J. Fent , Werner Heisenberg Inst., Max-Planck-Inst. fur Phys., Munchen, Germany
B. Dulny , Werner Heisenberg Inst., Max-Planck-Inst. fur Phys., Munchen, Germany
A. Osthoff , Werner Heisenberg Inst., Max-Planck-Inst. fur Phys., Munchen, Germany
W. Haberer , Werner Heisenberg Inst., Max-Planck-Inst. fur Phys., Munchen, Germany
pp. 197

Prototyping of a Biologically-Plausible Vision System for Robotic Applications (Abstract)

R. Zapata , Lab. d'Inf., de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Lepinay , Lab. d'Inf., de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
V. Creuze , Lab. d'Inf., de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
L. Torres , Lab. d'Inf., de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
J. Droulez , Lab. d'Inf., de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 202
Session 9-Digital Design

Hybrid latch Flip-Flop with Improved Power Efficiency (Abstract)

V.G. Oklobdzija , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
N. Nedovic , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
pp. 211

SisECO: Design of an Echo-Canceling IC for Base Band Modems (Abstract)

T. Campos , Microelectron. Group, Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
A. Prado , Microelectron. Group, Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
G. Stemmer , Microelectron. Group, Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
S. Bampi , Microelectron. Group, Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
R. Pacheco , Microelectron. Group, Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
R. Reis , Microelectron. Group, Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
L. Agostini , Microelectron. Group, Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
pp. 216

Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels (Abstract)

F.P. Cortes , Microelectron. Group, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
S. Bampi , Microelectron. Group, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
E.A.C. da Costa , Microelectron. Group, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
L. Carro , Microelectron. Group, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
R. Cardoso , Microelectron. Group, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 222

The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput (Abstract)

W.A.M. Van Noije , Escola Politecnica, Sao Paulo Univ., Brazil
J. Navarro , Escola Politecnica, Sao Paulo Univ., Brazil
pp. 228
Session 10-Fault Tolerant Design

Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy (Abstract)

D. Alexandrescu , TIMA Lab., Grenoble, France
L. Anghel , TIMA Lab., Grenoble, France
M. Nicolaidis , TIMA Lab., Grenoble, France
pp. 237

Optimized Generation of VHDL Mutants for Injection of Transition Errors (Abstract)

R. Leveugle , TIMA Lab., Inst. Nat. Polytech. de Grenoble, France
K. Hadjiat , TIMA Lab., Inst. Nat. Polytech. de Grenoble, France
pp. 243

Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis (Abstract)

A. Amory , Dept. of Electr. Eng., Catholic Univ.-PUCRS, Porto Alegre, Brazil
F. Vargas , Dept. of Electr. Eng., Catholic Univ.-PUCRS, Porto Alegre, Brazil
pp. 249
Session 11-Formal Methods and H/S Co-Design

JADE: An Embedded Systems Specification, Code Generation and Optimization Tool (Abstract)

L.L. Ambrosio , LECOM/DCC/UFMG, Fed. Univ. of Minas Gerais, Brazil
A.O. Fernandes , LECOM/DCC/UFMG, Fed. Univ. of Minas Gerais, Brazil
D.C. da Silva, Jr. , LECOM/DCC/UFMG, Fed. Univ. of Minas Gerais, Brazil
L.H. Canaan , LECOM/DCC/UFMG, Fed. Univ. of Minas Gerais, Brazil
C.J.N. Coelho, Jr. , LECOM/DCC/UFMG, Fed. Univ. of Minas Gerais, Brazil
R.G. Duarte , LECOM/DCC/UFMG, Fed. Univ. of Minas Gerais, Brazil
C.L. Pereira , LECOM/DCC/UFMG, Fed. Univ. of Minas Gerais, Brazil
pp. 263

An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification (Abstract)

V. Moraes Rodrigues , Lab. TIMA, Univ. Joseph Fourier, Grenoble, France
P. Georgelin , Lab. TIMA, Univ. Joseph Fourier, Grenoble, France
D. Borrione , Lab. TIMA, Univ. Joseph Fourier, Grenoble, France
pp. 269

A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System Design (Abstract)

S. Devadas , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
D.W. Engels , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 275

Design of a Classification System for Rectangular Shapes Using a Co-Design Environment (Abstract)

R.F. Molz , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
F.G. Moraes , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
L. Torres , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
M. Robert , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
P.M. Engel , Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 281
Session 12-Analog and Mixed-Signal Design

Fault Models and Compact Test Vectors for MOS OpAmp circuits (Abstract)

M.S. Lubaszewski , Brazilian Navy Res. Inst., Brazil
V.C. Alves , Brazilian Navy Res. Inst., Brazil
A.C. Mesquita , Brazilian Navy Res. Inst., Brazil
J.V. Calvano , Brazilian Navy Res. Inst., Brazil
pp. 289

Toward Analog Circuit Synthesis: A Global Methodology Based upon Design of Experiments (Abstract)

P. Fouillat , ENSERB, Bordeaux I Univ., France
Y. Deval , ENSERB, Bordeaux I Univ., France
J.-B. Begueret , ENSERB, Bordeaux I Univ., France
J. Tomas , ENSERB, Bordeaux I Univ., France
pp. 295

A JAVA-Based Mixed-Signal Design Environment (Abstract)

W. Ecker , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
A. Windisch , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
J. Mades , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
T. Schneider , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 301
Session 13-Physical Modeling

What is the Appropriate Model for Crosstalk Control? (Abstract)

L. Scheffer , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 315

Efficient /spl nu/MOS Realization of Threshold Voters for Self-Purging Redundancy (Abstract)

J.M. Quintana , Inst. de Microelectron., Centro Nacional de Microelectron., Seville, Spain
E. Rodriguez-Villegas , Inst. de Microelectron., Centro Nacional de Microelectron., Seville, Spain
M.J. Avedillo , Inst. de Microelectron., Centro Nacional de Microelectron., Seville, Spain
A. Rueda , Inst. de Microelectron., Centro Nacional de Microelectron., Seville, Spain
pp. 321

LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design (Abstract)

R. Reis , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
F.K. Ferreira , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
F. Moraes , Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 327

An Integrated Circuit for the in Situ Characterization of CMOS Best-Process Micromachining (Abstract)

K.S.J. Pister , Berkeley Sensor & Actuator Center, California Univ., Berkeley, CA, USA
B. Warneke , Berkeley Sensor & Actuator Center, California Univ., Berkeley, CA, USA
pp. 333
Session 14-Reconfigurable Hardware

An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing (Abstract)

J. Becker , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
T. Pionteck , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 341

Exploiting FPGA-Based Architectures and Design Tools for Problems of Reconfigurable Computations (Abstract)

I. Skliarova , Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
A.B. Ferrari , Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
pp. 347

Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnable (Abstract)

F. Galvez-Durand , Dept. of Comput. Sci., Mannheim Univ., Germany
J.M.S. de Alcantara , Dept. of Comput. Sci., Mannheim Univ., Germany
A.C.C. Vieira , Dept. of Comput. Sci., Mannheim Univ., Germany
H. Simmler , Dept. of Comput. Sci., Mannheim Univ., Germany
H. Singpiel , Dept. of Comput. Sci., Mannheim Univ., Germany
A. Kugel , Dept. of Comput. Sci., Mannheim Univ., Germany
R. Manner , Dept. of Comput. Sci., Mannheim Univ., Germany
V.C. Alves , Dept. of Comput. Sci., Mannheim Univ., Germany
pp. 359
Session 15-Low-Power, Low-Voltage

Limits to Voltage Scaling from the Low Power Perspective (Abstract)

M.R. Stan , Intel Corp., Dupont, WA, USA
A. Forestier , Intel Corp., Dupont, WA, USA
pp. 365

Adaptive Partial Businvert Encoding for Power Efficient Data Transfer over Wide System Buses (Abstract)

R. Siegmund , Dept. of Syst. & Circuit Design, Tech. Univ. Chemnitz, Germany
D. Muller , Dept. of Syst. & Circuit Design, Tech. Univ. Chemnitz, Germany
C. Kretzschmar , Dept. of Syst. & Circuit Design, Tech. Univ. Chemnitz, Germany
pp. 371

Energy-Efficient Register Access (Abstract)

J.H. Tseng , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
K. Asanovic , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 377
Session 16-Embedded Systems

Design and Simulation of Heterogeneous Embedded Systems (Abstract)

K.D. Mueller-Glaser , Res. Center for Inf. Technol., Karlsruhe Univ., Germany
M. Kuehl , Res. Center for Inf. Technol., Karlsruhe Univ., Germany
E. Sax , Res. Center for Inf. Technol., Karlsruhe Univ., Germany
W. Stork , Res. Center for Inf. Technol., Karlsruhe Univ., Germany
J. Drescher , Res. Center for Inf. Technol., Karlsruhe Univ., Germany
A. Wagner , Res. Center for Inf. Technol., Karlsruhe Univ., Germany
pp. 385

A Comparison of OO and Reactive Based Specifications on the Design of Embedded Systems (Abstract)

J.C.B. de Mattos , Comput. Sci., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
S.A. Ito , Comput. Sci., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
S.S. Toscani , Comput. Sci., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
L. Carro , Comput. Sci., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 391

A Comparison of Microcontrollers Targeted to FPGA-Based Embedded Applications (Abstract)

L. Carro , Inst. of Comput. Sci., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
S.A. Ito , Inst. of Comput. Sci., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 397

Author Index (PDF)

pp. 403
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