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2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) (2016)
Los Angeles, California, USA
Oct. 26, 2016 to Oct. 28, 2016
ISBN: 978-1-5090-6108-2
pp: 150-157
ABSTRACT
One of the main challenges in data center systems is operating under certain Quality of Service (QoS) while minimizing power consumption. Increasingly, data centers are adopting heterogeneous server architectures with different power-performance trade-offs. This requires careful understanding of the application behavior across multiple architectures at runtime so as to enable meeting specified power and performance requirements. In this work, we present and evaluate REPP-H (Runtime Estimation of Performance and Power on Heterogeneous data centers). REPP-H leverages hardware performance counters available on all major server architectures to ensure a highly responsive power capping mechanism and delivering a minimum performance in a single step. We experimentally show that REPP-H can successfully estimate power and performance of several single-threaded andmultiprogrammed workloads. The average errors on ARM, AMD and Intel architectures are, respectively, 7.1%, 9.0%, 7.1% when predicting performance, and 6.0%, 6.5%, 8.1% when predicting power on those heterogeneous servers.
INDEX TERMS
Computer architecture, Servers, Runtime, Power demand, Monitoring, Predictive models, Ports (Computers),performance monitoring counters, Power, Performance, modeling, heterogeneity, dynamic voltage and frequency scaling
CITATION
Rajiv Nishtala, Xavier Martorell, Vinicius Petrucci, Daniel Mosse, "REPP-H: Runtime Estimation of Power and Performance on Heterogeneous Data Centers", 2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), vol. 00, no. , pp. 150-157, 2016, doi:10.1109/SBAC-PAD.2016.27
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