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Computer Architecture and High Performance Computing, Symposium on (2012)
New York, NY, USA USA
Oct. 24, 2012 to Oct. 26, 2012
ISSN: 1550-6533
ISBN: 978-1-4673-4790-7
pp: 286-293
Chip multiprocessors (CMPs) are becoming the common choice to implement embedded systems due to they achieve a good tradeoff between performance and power. Because of manufacturability reasons, CMPs use to implement one or several memory controllers, each one shared by a set of cores. Thus, memory requests from distinct cores compete among them when accessing to memory. This means that the memory access latency can widely vary depending on the co-runners and the memory controller scheduling policy, thus yielding to unpredictable behavior. This work focuses on the design of a memory controller to support workloads with real-time constraints, both hard real-time (HRT) and soft real-time (SRT) applications. These systems must guarantee the execution of HRT applications while improving the performance of the SRT applications. In this paper we propose two memory controller policies for multicore embedded systems: HR-first and ATR-first. The former prioritizes memory requests of HRT tasks, achieving important energy savings but poor performance for SRT applications. The latter gives priority to those HRT requests that are critical to guarantee schedulability. Results show that the ATR-first policy presents similar energy consumption as the HR-first policy while reducing the number of SRT deadline misses around 49%, on average, and reaching the fulfillment of all deadlines in some scenarios.
Quality of Service, Memory Access, Multicore Systems, Real-Time

J. L. March, S. Petit, J. Sahuquillo, H. Hassan and J. Duato, "Efficiently Handling Memory Accesses to Improve QoS in Multicore Systems under Real-Time Constraints," Computer Architecture and High Performance Computing, Symposium on(SBAC-PAD), New York, NY, USA USA, 2012, pp. 286-293.
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