Computer Architecture and High Performance Computing, Symposium on (2012)

New York, NY, USA USA

Oct. 24, 2012 to Oct. 26, 2012

ISSN: 1550-6533

ISBN: 978-1-4673-4790-7

pp: 67-74

ABSTRACT

The rising popularity of graphics processing units is bringing renewed interest in code optimization techniques for SIMD processors. Many of these optimizations rely on divergence analyses, which classify variables as uniform, if they have the same value on every thread, or divergent, if they might not. This paper introduces a new kind of divergence analysis, that is able to represent variables as affine functions of thread identifiers. We have implemented this analysis in Ocelot, an open source compiler, and use it to analyze a suite of 177 CUDA kernels from well-known benchmarks. We can mark about one fourth of all program variables as affine functions of thread identifiers. In addition to the novel divergence analysis, we also introduce the notion of a divergence aware register allocator. This allocator uses information from our analysis to either rematerialize affine variables, or to move uniform variables to shared memory. As a testimony of its effectiveness, our divergence aware allocator produces GPU code that is 29.70% faster than the code produced by Ocelot's register allocator. Divergence analysis with affine constraints is publicly available in the Ocelot compiler since June/2012.

INDEX TERMS

Divergence, GPU, SIMD

CITATION

D. Sampaio, R. Martins, S. Collange and F. M. Pereira, "Divergence Analysis with Affine Constraints,"

*Computer Architecture and High Performance Computing, Symposium on(SBAC-PAD)*, New York, NY, USA USA, 2012, pp. 67-74.

doi:10.1109/SBAC-PAD.2012.22

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