Computer Architecture and High Performance Computing, Symposium on (2011)
Vitoria, Espirito Santo Brazil
Oct. 26, 2011 to Oct. 29, 2011
Probability-based approaches for phylogenetic inference, like Maximum Likelihood (ML) and Bayesian Inference, provide the most accurate estimate of evolutionary relationships among species. But they come at a high algorithmic and computational cost. Network-on-chip (NoC), being an emerging paradigm, has not been explored yet to achieve fine-grained parallelism for these applications. In this paper, we present the design and performance evaluation of an NoC architecture for RAxML, which is one of the most widely used ML software suites. Specifically, we implement the top three function kernels that account for more than 85% of the total run-time. Simulations show that through novel core design, allocation and placement strategies our NoC-based implementation can achieve function-level speedups of 388x to 786x and system-level speedups in excess of 5000x over state-of-the-art multithreaded software.
Network-on-Chip, phylogeny reconstruction, hardware accelerator, multi-core
Ananth Kalyanaraman, Turbo Majumder, Partha Pande, "Accelerating Maximum Likelihood Based Phylogenetic Kernels Using Network-on-Chip", Computer Architecture and High Performance Computing, Symposium on, vol. 00, no. , pp. 17-24, 2011, doi:10.1109/SBAC-PAD.2011.17