Computer Architecture and High Performance Computing, Symposium on (2009)
Sao Paolo, Brazil
Oct. 28, 2009 to Oct. 31, 2009
The rise in multi-core architectures has led to the abundance of computing resources on a chip. Virtualization has emerged as a way to efficiently partition and share these resources. Thus, the emphasis in micro-architecture design, especially in x86, has shifted towards providing hardware support for better performance of VMs on bare metal. One of the areas of focus for these efforts is the Translation Lookaside Buffer (TLB). Recent modifications in the TLB include the addition of tags as a part of the TLB entry and the incorporation of hardware primitives to perform tag comparison during TLB lookup. In this paper we present the Tag Manager Table (TMT), a low-latency management architecture for tagging the TLB entries using process-specific identifiers (based on the CR3 register in x86), and thereby reducing the number of flushes and the miss rate in the TLB. Using a full system simulation approach, we investigate the performance benefit of these tags and explore how it varies with the size of the TMT, the TLB architecture and the workload characteristics. We also perform a sensitivity analysis and quantify the relative importance of all these factors in determining the benefit from CR3 tagging. While our focus is on virtualized platforms, this approach is equally applicable for non virtualized environments.
G. Venkatasubramanian, D. Newell, R. J. Figueiredo and R. Illikkal, "TMT - A TLB Tag Management Framework for Virtualized Platforms," Computer Architecture and High Performance Computing, Symposium on(SBAC-PAD), Sao Paolo, Brazil, 2009, pp. 153-160.