The Community for Technology Leaders
Computer Architecture and High Performance Computing, Symposium on (2009)
Sao Paolo, Brazil
Oct. 28, 2009 to Oct. 31, 2009
ISSN: 1550-6533
ISBN: 978-0-7695-3857-0
pp: 35-40
Low Density Parity Check (LDPC) code is an error correction code that can achieve performance close to Shannon limit and inherently suitable for parallel implementation. It has been widely adopted in various communication standards such as DVB-S2, WiMAX, and Wi-Fi. However, the irregular message exchange pattern is a major challenge in LDPC decoder implementation In addition, faced with an era that diverse applications are integrated in a single system, a flexible, scalable, efficient and cost-effective implementation of LDPC decoder is highly preferable. In this paper, we proposed a multi-processor platform based on network-on-chip (NoC) interconnect as a solution to these problems. By using a distributed and cooperative way for LDPC decoding, the memory bottleneck commonly seen in LDPC decoder design is eliminated. Simulation results from long LDPC codes with various code rates show good scalability and speedups are obtained by our approach.
LDPC decoder, network-on-chip, multiprocessor, parallel processing

N. Bagherzadeh, W. Hu and J. H. Bahn, "Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform," Computer Architecture and High Performance Computing, Symposium on(SBAC-PAD), Sao Paolo, Brazil, 2009, pp. 35-40.
87 ms
(Ver 3.3 (11022016))