The Community for Technology Leaders
Computer Architecture and High Performance Computing, Symposium on (2009)
Sao Paolo, Brazil
Oct. 28, 2009 to Oct. 31, 2009
ISSN: 1550-6533
ISBN: 978-0-7695-3857-0
pp: 3-10
Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers and to master hardware description languages (HDLs) such as VHDL or Verilog. The attempts to furnish a high-level compilation flow (e.g., from C programs) still have open issues before efficient and consistent results can be obtained. Bearing in mind the FPGA resources, we have developed LALP, a novel language to program FPGAs. A compilation framework including mapping capabilities supports the language. The main ideas behind LALP is to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to permit the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. In this paper we describe LALP, and show how it can be used to achieve high-performance computing solutions.
FPGA, Compilers, ALP, LALP

E. Marques, R. Menotti, J. M. Cardoso and M. M. Fernandes, "LALP: A Novel Language to Program Custom FPGA-Based Architectures," Computer Architecture and High Performance Computing, Symposium on(SBAC-PAD), Sao Paolo, Brazil, 2009, pp. 3-10.
83 ms
(Ver 3.3 (11022016))