Message from the General Chairs (PDF)

19th International Symposium on Computer Architecture and High Performance Computing - Cover (PDF)

19th International Symposium on Computer Architecture and High Performance Computing - Copyright (PDF)

Program Committee (PDF)

Reviewers (PDF)

Brazilian Computer Society (SBC) (PDF)

Multi-level Parallelism in the Computational Modeling of the Heart (Abstract)

Computational Characteristics of Production Seismic Migration and its Performance on Novel Processor Architectures (Abstract)

Voice Command Recognition with Dynamic Time Warping (DTW) using Graphics Processing Units (GPU) with Compute Unified Device Architecture (CUDA) (Abstract)

Exploring Novel Parallelization Technologies for 3-D Imaging Applications (Abstract)

Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor (Abstract)

Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units (Abstract)

Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications (Abstract)

Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors (Abstract)

Performance Improvement of the Parallel Lattice Boltzmann Method Through Blocked Data Distributions (Abstract)

A Multigrid-Schwarz Method for the Solution of Hydrodynamics and Heat Transfer Problems in Unstructured Meshes (Abstract)

Performance Evaluation of the Dual-Core Based SGI Altix 4700 (Abstract)

Impacts of Multiprocessor Configurations on Workloads in Bioinformatics (Abstract)

Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning (Abstract)

Optimized Math Functions for a Fixed-Point DSP Architecture (Abstract)

A Component-Oriented Support for Hierarchical MPI Programming on Multi-Cluster Grid Environments (Abstract)

A Selector of Grid Resources based on the Semantic Integration of Multiple Ontologies (Abstract)

A Novel Algorithm for Indirect Reputation-Based Grid Resource Management (Abstract)

Register File Energy Optimization for Snooping Based Clustered VLIW Architectures (Abstract)

Queue Register File Optimization Algorithm for QueueCore Processor (Abstract)

An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance (Abstract)

A Code Compression Method to Cope with Security Hardware Overheads (Abstract)

Architectural Breakdown of End-to-End Latency in a TCP/IP Network (Abstract)

Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms (Abstract)

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP) (Abstract)

Node Level Primitives for Parallel Exact Inference (Abstract)

Fault-tolerance in filter-labeled-stream applications (Abstract)

High-Level Service Connectors for Component-Based High Performance Computing (Abstract)

On-line Scheduling of MPI-2 Programs with Hierarchical Work Stealing (Abstract)

Exigency-based real-time scheduling policy to provide absolute QoS for web services (Abstract)

DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems (Abstract)

Automatic Constraint Partitioning to Speed Up CLP Execution (Abstract)

Author Index (PDF)