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Computer Architecture and High Performance Computing, Symposium on (2006)
Ouro Preto, MG, Brazil
Oct. 17, 2006 to Oct. 20, 2006
ISSN: 1550-6533
ISBN: 0-7695-2704-3
pp: 107-116
Ram Srinivasan , New Mexico State University, Los Alamos National Laboratory, USA
Jeanine Cook , New Mexico State University, Los Alamos National Laboratory, USA
Olaf Lubeck , New Mexico State University, Los Alamos National Laboratory, USA
ABSTRACT
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been extensively used due to their inherent accuracy and flexibility. However, the effort involved in building them, their slow speed, and their limited ability to provide insight often imposes constraints on the extent of design exploration. In this paper, we refine our earlier Monte Carlo based CPI prediction model [11] to include software assisted data-prefetching and an improved memory model. Softwarebased prefetching is becoming an increasingly important feature in modern processors but to the best of our knowledge, existing frameworks do not model it. Our model uses microarchitecture independent application characteristics to predict CPI with an average error of less than 10% when vaidated against the Itanium-2 processor. Besides accurate performance prediction, we illustrate the applications of the model to processor bottle-neck analysis, workload characterization and design space exploration.
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CITATION

R. Srinivasan, J. Cook and O. Lubeck, "Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach," Computer Architecture and High Performance Computing, Symposium on(SBAC-PAD), Ouro Preto, MG, Brazil, 2006, pp. 107-116.
doi:10.1109/SBAC-PAD.2006.31
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