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Computer Architecture and High Performance Computing, Symposium on (2005)
Rio de Janeiro, Brazil
Oct. 24, 2005 to Oct. 27, 2005
ISSN: 1550-6533
ISBN: 0-7695-2446-X
pp: 201-208
Jose R. Brunheroto , IBM Thomas J. Watson Research Center
Valentina Salapura , IBM Thomas J. Watson Research Center
Fernando F. Redigolo , IBM Thomas J. Watson Research Center
Dirk Hoenicke , IBM Thomas J. Watson Research Center
Alan Gara , IBM Thomas J. Watson Research Center
ABSTRACT
<p>Scientific applications exhibit good spatial and temporal data memory access locality. It is possible to hide memory latency for the Level 3 cache, and reduce contention between multiple cores sharing a single Level 3 cache, by using a prefetch cache to identify data streams which can be profitably prefetched, and decouple the cache line size mismatch between L3 cache and the Level 1 data cache. In this work, a design space exploration is presented, which helped shape the design of the BlueGene/L supercomputer memory sub-system. The prefetch cache consists of a small number of 128 line buffers that speculatively prefetches data from the L3 cache, since applications present some sequential access pattern, this prefetching scheme increases the likelyhood that a request from the Level 1 data cache will be present in the prefetch cache.</p> <p>Since most compute intensive applications contain a small number of data streams, it is sufficient for the prefetch cache to have small number of line buffers to track and detect the data streams. This paper focuses on the evaluation of stream detection mechanismis and the influence of varying the replacement policies for stream prefetch caches.</p>
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CITATION

V. Salapura, D. Hoenicke, J. R. Brunheroto, F. F. Redigolo and A. Gara, "Data cache prefetching design space exploration for BlueGene/L supercomputer," Computer Architecture and High Performance Computing, Symposium on(SBAC-PAD), Rio de Janeiro, Brazil, 2005, pp. 201-208.
doi:10.1109/CAHPC.2005.23
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