The Community for Technology Leaders
Application Specific Processors, Symposium on (2011)
San Diego, CA, USA
June 5, 2011 to June 6, 2011
ISBN: 978-1-4577-1212-8
TABLE OF CONTENTS
Papers

[Title page] (Abstract)

pp. i-vii

How sensitive is processor customization to the workload's input datasets? (Abstract)

Chengyong Wu , ICT, Beijing, China
Zheng Li , INRIA, France
Stijn Eyerman , Ghent University, Belgium
Lieven Eeckhout , Ghent University, Belgium
Olivier Temam , INRIA, France
Maximilien Breughe , Ghent University, Belgium
Yang Chen , ICT, Beijing, China
pp. 1-7

TARCAD: A template architecture for reconfigurable accelerator designs (Abstract)

Eduard Ayguade , Computer Sciences, Barcelona Supercomputing Center, Spain
Nacho Navarro , Dept. Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
Muhammad Shafiq , Computer Sciences, Barcelona Supercomputing Center, Spain
Miquel Pericas , Computer Sciences, Barcelona Supercomputing Center, Spain
pp. 8-15

Customized MPSoC synthesis for task sequence (Abstract)

Nicolas Boichat , Department of Computer Science, National University of Singapore, Singapore
Liang Chen , Department of Computer Science, National University of Singapore, Singapore
Tulika Mitra , Department of Computer Science, National University of Singapore, Singapore
pp. 16-21

Integrating formal verification and high-level processor pipeline synthesis (Abstract)

Shih-Lien L. Lu , Intel Corporation, USA
Eriko Nurvitadhi , Carnegie Mellon University, USA
James C. Hoe , Carnegie Mellon University, USA
Timothy Kam , Intel Corporation, USA
pp. 22-29

USHA: Unified software and hardware architecture for video decoding (Abstract)

Hristo Nikolov , Leiden Institute of Advanced Computer Science (LIACS), Leiden University, The Netherlands
S. K. Nandy , Computer Aided Design Laboratory (CADL), Indian Institute of Science, Bangalore, India
Adarsha Rao , Computer Aided Design Laboratory (CADL), Indian Institute of Science, Bangalore, India
Ed F. Deprettere , Leiden Institute of Advanced Computer Science (LIACS), Leiden University, The Netherlands
pp. 30-37

Modular high-throughput and low-latency sorting units for FPGAs in the Large Hadron Collider (Abstract)

Katherine Compton , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 53706, USA
Anthony Gregerson , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 53706, USA
Michael Schulte , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 53706, USA
Amin Farmahini-Farahani , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 53706, USA
pp. 38-45

Memory-efficient volume ray tracing on GPU for radiotherapy (Abstract)

Danny Z. Chen , Department of Computer Science and Engineering, University of Notre Dame, Indiana, USA
X. Sharon Hu , Department of Computer Science and Engineering, University of Notre Dame, Indiana, USA
Bo Zhou , Department of Radiation Oncology, University of Maryland School of Medicine, Baltimore, USA
pp. 46-51

System integration of Elliptic Curve Cryptography on an OMAP platform (Abstract)

Patrick Schaumont , ECE Department, Virginia Tech, Blacksburg, 24061, USA
Christian Tergino , ECE Department, Virginia Tech, Garden City Park, NY 11040, USA
Sergey Morozov , ECE Department, Virginia Tech, Blacksburg, 24061, USA
pp. 52-57

ISIS: An accelerator for Sphinx speech recognition (Abstract)

Jenny X. Chang , Intel Corporation, Santa Clara, CA 95052 USA
Anthony Chun , Intel Corporation, Santa Clara, CA 95052 USA
Ravishankar Iyer , Intel Corporation, Santa Clara, CA 95052 USA
Michael Deisher , Intel Corporation, Santa Clara, CA 95052 USA
Zhen Fang , Intel Corporation, Santa Clara, CA 95052 USA
pp. 58-61

Dynamically reconfigurable architecture for a driver assistant system (Abstract)

Yassin El Hillali , University of Valenciennes, France
Rabie Ben Atitallah , University of Valenciennes, France
Smail Niar , University of Valenciennes, France
Mazen A. R. Saghir , Texas A&M University at Qatar, USA
Naim Harb , University of Valenciennes, France
pp. 62-65

FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm (Abstract)

Daniel L. Lau , Department of Electrical and Computer Engineering, University of Kentucky, Lexington, 40506, USA
J. Robert Heath , Department of Electrical and Computer Engineering, University of Kentucky, Lexington, 40506, USA
Rishvanth Kora Venugopal , Department of Electrical and Computer Engineering, University of Kentucky, Lexington, 40506, USA
pp. 66-69

3D recursive Gaussian IIR on GPU and FPGAs -- A case for accelerating bandwidth-bounded applications (Abstract)

Jason Cong , Computer Science Department, University of California, Los Angeles, 90095, USA
Yi Zou , Computer Science Department, University of California, Los Angeles, 90095, USA
Muhuan Huang , Computer Science Department, University of California, Los Angeles, 90095, USA
pp. 70-73

A fast CUDA implementation of agrep algorithm for approximate nucleotide sequence matching (Abstract)

Hongjian Li , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong
Bing Ni , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong
Kwong-Sak Leung , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong
Man-Hon Wong , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong
pp. 74-77

Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration (Abstract)

Frank Hannig , Department of Computer Science, University of Erlangen-Nuremberg, Germany
Mario Korner , Siemens Healthcare Sector, Forchheim, Germany
Jurgen Teich , Department of Computer Science, University of Erlangen-Nuremberg, Germany
Richard Membarth , Department of Computer Science, University of Erlangen-Nuremberg, Germany
Wieland Eckert , Siemens Healthcare Sector, Forchheim, Germany
pp. 78-81

A massively parallel implementation of QC-LDPC decoder on GPU (Abstract)

Michael Wu , Department of Electrical and Computer Engineer, Rice University, Houston, Texas 77005, USA
Joseph R. Cavallaro , Department of Electrical and Computer Engineer, Rice University, Houston, Texas 77005, USA
Guohui Wang , Department of Electrical and Computer Engineer, Rice University, Houston, Texas 77005, USA
Yang Sun , Department of Electrical and Computer Engineer, Rice University, Houston, Texas 77005, USA
pp. 82-85

ARTE: An Application-specific Run-Time management framework for multi-core systems (Abstract)

Gianluca Palermo , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
Cristina Silvano , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
Vittorio Zaccaria , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
Giovanni Mariani , ALaRI - University of Lugano, Switzerland
pp. 86-93

A hardware acceleration technique for gradient descent and conjugate gradient (Abstract)

Biplab Deka , Department of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, USA
David Kesler , Department of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, USA
Rakesh Kumar , Department of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, USA
pp. 94-101

A multi-threaded coarse-grained array processor for wireless baseband (Abstract)

Praveen Raghavan , IMEC, Kapeldreef 75, Leuven, Belgium
Tom Vander Aa , IMEC, Kapeldreef 75, Leuven, Belgium
Antoine Dejonghe , IMEC, Kapeldreef 75, Leuven, Belgium
Martin Palkovic , IMEC, Kapeldreef 75, Leuven, Belgium
Liesbet Van der Perre , IMEC, Kapeldreef 75, Leuven, Belgium
Matthias Hartmann , IMEC, Kapeldreef 75, Leuven, Belgium
pp. 102-107

Hardware/software co-designed accelerator for vector graphics applications (Abstract)

Chih-Tsun Huang , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30013
Hsin-Wen Wei , Institute of Infromation Science, Academia Sinica, Taipei, Taiwan 115
Yeh-Ching Chung , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30013
Yi-Cheng Chen , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30013
Shuo-Hung Chen , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30013
Hsiao-Mei Lin , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30013
pp. 108-114

Scalable object detection accelerators on FPGAs using custom design space exploration (Abstract)

Chen Huang , Dept. of Computer Science and Engineering, University of California, Riverside, USA
Frank Vahid , Dept. of Computer Science and Engineering, University of California, Riverside, USA
pp. 115-121

A parallel accelerator for semantic search (Abstract)

Srimat T. Chakradhar , NEC Laboratories America, Inc., Princeton, NJ, USA
Abhinandan Majumdar , NEC Laboratories America, Inc., Princeton, NJ, USA
Hans Peter Graf , NEC Laboratories America, Inc., Princeton, NJ, USA
Srihari Cadambi , NEC Laboratories America, Inc., Princeton, NJ, USA
pp. 122-128

A novel parallel Tier-1 coder for JPEG2000 using GPUs (Abstract)

Iris R. Bahar , School of Engineering, Brown University, Providence, RI 02912, USA
Joseph L. Mundy , School of Engineering, Brown University, Providence, RI 02912, USA
Roto Le , School of Engineering, Brown University, Providence, RI 02912, USA
pp. 129-136
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