RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003 (2003)
Dec. 3, 2003 to Dec. 5, 2003
Bilge E. S. Akgul , Georgia Institute of Technology, Atlanta
Vincent J. Mooney III , Georgia Institute of Technology, Atlanta
Henrik Thane , Malardalen University, Vasteras, Sweden
Pramote Kuacharoen , Georgia Institute of Technology, Atlanta
Previous work has shown that a system-on-a-chip lock cache (SoCLC) reduces on-chip memory traffic, provides a fair and fast lock hand-off, simplifies software, increases the real-time predictability of the system and improves performance. In this research work, we extend the SoCLC mechanism with a priority inheritance support implemented in hardware. Priority inheritance provides a higher level of real-time guarantees for synchronizing application tasks. Experimental results indicate that our SoCLC hardware mechanism with priority inheritance achieves a 36% speedup in lock delay, 88% speedup in lock latency and 15% speedup in the overall execution time when compared to its software counterpart. The cost in terms of additional hardware area for the SoCLC with priority inheritance is approximately 10,000 NAND2 gates.
H. Thane, V. J. Mooney III, P. Kuacharoen and B. E. Akgul, "Hardware Support for Priority Inheritance," RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003(RTSS), Cancun, Mexico, 2003, pp. 246.