CSDL Home R RTAS 2013 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)
April 9, 2013 to April 11, 2013
A. Banerjee , Nat. Univ. of Singapore, Singapore, Singapore
S. Chattopadhyay , Nat. Univ. of Singapore, Singapore, Singapore
A. Roychoudhury , Nat. Univ. of Singapore, Singapore, Singapore
Hard real-time systems are required to meet critical deadlines. Worst case execution time (WCET) is therefore an important metric for the system level schedulability analysis of hard real-time systems. However, performance enhancing features of a processor (e.g. pipeline, caches) makes WCET analysis a very difficult problem. In this paper, we propose a novel approach to combine abstract interpretation (AI) and satisfiability (SAT) checking (hence the name AI+SAT) for different varieties of micro-architectural modeling. Our work in this paper is inspired by the research advances in program flow analysis(e.g. infeasible path analysis). We show that the accuracy of WCET estimates can be improved in a scalable fashion by using SAT checkers to integrate infeasible path analysis results into micro-architectural modeling. Our modeling is implemented on top of the Chronos WCET analysis tool and we improve the accuracy of WCET estimates for instruction cache, data cache, branch predictors and shared caches.
Abstracts, Analytical models, Computational modeling, Equations, Real-time systems, Transfer functions, Artificial intelligence,
A. Banerjee, S. Chattopadhyay, A. Roychoudhury, "Precise micro-architectural modeling for WCET analysis via AI+SAT", RTAS, 2013, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS) 2013, pp. 87-96, doi:10.1109/RTAS.2013.6531082