2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS) (2013)
Philadelphia, PA, USA USA
Apr. 9, 2013 to Apr. 11, 2013
R. Mancuso , Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
R. Dudko , Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
E. Betti , Univ. of Rome “Tor Vergata”, Rome, Italy
M. Cesati , Univ. of Rome “Tor Vergata”, Rome, Italy
M. Caccamo , Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
R. Pellizzoni , Univ. of Waterloo, Waterloo, ON, Canada
Multi-core architectures are shaking the fundamental assumption that in real-time systems the WCET, used to analyze the schedulability of the complete system, is calculated on individual tasks. This is not even true in an approximate sense in a modern multi-core chip, due to interference caused by hardware resource sharing. In this work we propose (1) a complete framework to analyze and profile task memory access patterns and (2) a novel kernel-level cache management technique to enforce an efficient and deterministic cache allocation of the most frequently accessed memory areas. In this way, we provide a powerful tool to address one of the main sources of interference in a system where the last level of cache is shared among two or more CPUs. The technique has been implemented on commercial hardware and our evaluations show that it can be used to significantly improve the predictability of a given set of critical tasks.
Resource management, Interference, Real-time systems, Memory management, Hardware, Instruments, Kernel
R. Mancuso, R. Dudko, E. Betti, M. Cesati, M. Caccamo and R. Pellizzoni, "Real-time cache management framework for multi-core architectures," 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), Philadelphia, PA, USA USA, 2013, pp. 45-54.