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Rapid System Prototyping, IEEE International Workshop on (2007)
Porto Alegre, RS, Brazil
May 28, 2007 to May 30, 2007
ISSN: 1074-6005
ISBN: 0-7695-2834-1
TABLE OF CONTENTS
Introduction
Session 1: Co-design

Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass (Abstract)

Pablo Viana , Federal University of Alagoas, Brazil
Edna Barros , Federal University of Pernambuco, Brazil
Andre Silva , Federal University of Pernambuco, Brazil
Guilherme Esmeraldo , Federal University of Pernambuco, Brazil
pp. 3-9

Codesign of a Computationally Intensive Problem in GF(3) (Abstract)

Kenneth B. Kent , University of New Brunswick
Micaela Serra , University of Victoria
Beatriz C. Iaderoza , University of Victoria
pp. 10-16

Unified Inter-Communication Architecture for Systems-on-Chip (Abstract)

J. Barba , University of Castilla-La Mancha
J.C. Lopez , University of Castilla-La Mancha
F. Rincon , University of Castilla-La Mancha
F.J. Villanueva , University of Castilla-La Mancha
D. Villa , University of Castilla-La Mancha
J. Dondo , University of Castilla-La Mancha
F. Moya , University of Castilla-La Mancha
pp. 17-26
Session 2: HW Performance

SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems (Abstract)

Ney Calazans , PUCRS, Brazil
Guilherme Guindani , PUCRS, Brazil
Fernando Moraes , PUCRS, Brazil
Hugo Schmitt , PUCRS, Brazil
Luis Carlos Caruso , PUCRS, Brazil
pp. 27-33

Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs (Abstract)

Ney Calazans , Pontif?cia Universidade Cat?lica do Rio Grande do Sul (PUCRS)
Ewerson Carvalho , Pontif?cia Universidade Cat?lica do Rio Grande do Sul (PUCRS)
Fernando Moraes , Pontif?cia Universidade Cat?lica do Rio Grande do Sul (PUCRS)
pp. 34-40

Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem (Abstract)

Dionisios Pnevmatikatos , Technical University of Crete (TUC)
Ioannis Mavroidis , Technical University of Crete (TUC)
Ioannis Papaefstathiou , Technical University of Crete (TUC)
pp. 41-47

Hardware/Firmware Verification of Graphic IP (Abstract)

Kamdem Romain , STMicroelectronics
pp. 48-56
Session 3: Short Papers FPGA - Applications

Communication Models in Networks-on-Chip (Abstract)

Aline Mello , PUCRS, Brazil
Everton Carara , PUCRS, Brazil
Fernando Moraes , PUCRS, Brazil
pp. 57-60

A Lightweight Framework for Runtime Reconfigurable System Prototyping (Abstract)

Thilo Pionteck , University of Luebeck
Roman Koch , University of Luebeck
Erik Maehle , University of Luebeck
Carsten Albrecht , University of Luebeck
pp. 61-64

Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System (Abstract)

V. Mariatos , Diaplous Machine Vision
K.D. Adaos , University of Patras
G.P. Alexiou , University of Patras
pp. 65-68

Object-Oriented Reconfiguration (Abstract)

Antonio Carlos S. Beck , UFRGS, Brazil
Luigi Carro , UFRGS, Brazil
Julio C. B. Mattos , UFRGS, Brazil
pp. 69-74
Session 4: Formal Specification

A Semantics for UML-RT using n-calculus (Abstract)

Celso Massaki Hirata , Instituto Tecnol?gico de Aeron?utica - ITA, Brazil
Juliana de Melo Bezerra , Instituto Tecnol?gico de Aeron?utica - ITA, Brazil
pp. 75-82

Rapid Prototyping of Intrusion Detection Systems (Abstract)

Fabrice Kordon , Universit? Pierre, Cedex, France
Jean-Baptiste Voron , Universit? Pierre, Cedex, France
pp. 89-98
Session 5: Prototyping and Development Methodologies and Tools

A Tailored Design Partitioning Method for Hardware Emulation (Abstract)

W. Hardt , Chemnitz University of Technology
T. Fuchs , Fraunhofer IIS, Design Automation Division
St. Ruelke , Fraunhofer IIS, Design Automation Division
R. Beckert , Fraunhofer IIS, Design Automation Division
pp. 99-105

Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels (Abstract)

Pier Stanislao Paolucci , ATMEL Roma Advanced DSP, Italy
Xavier Guerin , TIMA Laboratory, France
Ahmed Jerraya , CEA-LETI, MINATEC, France
Katalin Popovici , TIMA Laboratory, France
Frederic Rousseau , TIMA Laboratory, France
pp. 113-122
Session 6: Testing

A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation (Abstract)

Guido Araujo , State University of Campinas, Brazil
Alexandro Baldassin , State University of Campinas, Brazil
Fernando Kronbauer , State University of Campinas, Brazil
Sandro Rigo , State University of Campinas, Brazil
Bruno Albertini , State University of Campinas, Brazil
Paulo Centoducatte , State University of Campinas, Brazil
Rodolfo Azevedo , State University of Campinas, Brazil
pp. 123-129

Nonintrusive Black- and White-Box Testing of Embedded Systems Software against UML Models (Abstract)

Philipp Graf , University of Karlsruhe
Clemens Reichmann , University of Karlsruhe
Klaus D. Muller-Glaser , University of Karlsruhe
pp. 130-138
Session 7: Short Papers - HW Performance, Co-Design and Tool

Architectural Issues in Homogeneous NoC-Based MPSoC (Abstract)

Nicolas Saint-Jean , LIRMM, France
Ismael Grehs , PUCRS, Brazil
Gilles Sassatelli , LIRMM, France
Fernando Moraes , PUCRS, Brazil
Cristiane Woszezenki , PUCRS, Brazil
pp. 139-142

Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures (Abstract)

Zhonghai Lu , Royal Institute of Technology, Sweden
Axel Jantsch , Royal Institute of Technology, Sweden
Jonas Sicking , Royal Institute of Technology, Sweden
Ingo Sander , Royal Institute of Technology, Sweden
pp. 143-149

Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers (Abstract)

Himanshu Arora , Marvell Semiconductor
Nikolaus Klemmer , Ericsson Mobile Platforms
Thomas Jochum , Duke University
Patrick Wolf , Duke University
pp. 150-156
Session 8: Short Papers - Formal Specification

Behavioral synthesis of property specification language (PSL) assertions (Abstract)

Markus Pfaff , University of Applied Sciences, Austria
Harald Obereder , University of Applied Sciences, Austria
pp. 157-160

Structured Approach to Property Specification and Verification of HW IP (Abstract)

Anthony McIsaac , STMicroelectronics, UK
Lyes Benalycherif , STMicroelectronics, France
Neil Dunlop , STMicroelectronics, UK
pp. 161-166
Session 9: Applications

A CABAC Encoder Design of H.264/AVC with RDO Support (Abstract)

Y. Lian , National University of Singapore
B.L. Ho , National University of Singapore
Thinh M. Le , National University of Singapore
X.H. Tian , National University of Singapore
pp. 167-173

FPGA Prototyping Strategy for a H.264/AVC Video Decoder (Abstract)

Bruno Zatt , Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Vagner S. Rosa , Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Luciano V. Agostini , Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Arnaldo Azevedo , Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Roger E. Porto , Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Wagston T. Staehler , Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Sergio Bampi , Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Altamiro A. Susin , Universidade Fed. de Pelotas Pelotas, RS, Brazil
pp. 174-180

ER-EDF: A QoS Scheduler for Real-Time Embedded Systems (Abstract)

C?sar A. M. Marcon , PPGCC - FACIN - PUCRS, Brazil
David , PPGCC - FACIN - PUCRS, Brazil
Fabiano Hessel , PPGCC - FACIN - PUCRS, Brazil
pp. 181-188
Session 10: FPGA and SW Algorithms

Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors (Abstract)

K. Karuri , RWTH Aachen University 52056 Aachen, Germany
H. Meyr , RWTH Aachen University 52056 Aachen, Germany
G. Ascheid , RWTH Aachen University 52056 Aachen, Germany
R. Leupers , RWTH Aachen University 52056 Aachen, Germany
Z. Rakosi , RWTH Aachen University 52056 Aachen, Germany
A. Chattopadhyay , RWTH Aachen University 52056 Aachen, Germany
D. Kammler , RWTH Aachen University 52056 Aachen, Germany
pp. 189-194

Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes (Abstract)

Kiyoung Choi , Seoul National Univ.
Nacer-Eddine Zergainoh , TIMA Laboratory, France
Ahmed A. Jerraya , CEA-LETI, MINATEC, France
Youngchul Cho , Seoul National Univ.
pp. 195-201

A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications (Abstract)

Myoung-Soo Jung , SAMSUNG Electronics. Co., Ltd., KOREA
Yangsup Lee , SAMSUNG Electronics. Co., Ltd., KOREA
Hanbin Yoon , SAMSUNG Electronics. Co., Ltd., KOREA
Wonhee Cho , SAMSUNG Electronics. Co., Ltd., KOREA
Wonmoon Cheon , SAMSUNG Electronics. Co., Ltd., KOREA
Chanik Park , SAMSUNG Electronics. Co., Ltd., KOREA
pp. 202-208
Author Index

Author Index (PDF)

pp. 209
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