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Rapid System Prototyping, IEEE International Workshop on (2004)
Geneva, Switzerland
June 28, 2004 to June 30, 2004
ISSN: 1074-6005
ISBN: 0-7695-2159-2

RSP 2004 (PDF)

pp. 0_2
Keynote Speech
Session 1: Formal Specification and Verification

Automated Hardware Synthesis from Formal Specification Using SAT Solvers (Abstract)

David Greaves , University of Cambridge/Tenison EDA
pp. 15-20

ASET: A Formal Model for System Emulation and Verification (Abstract)

Swapan Bhattacharyya , Jadavpur University
Joydeep Bhattacharyya , Jadavpur University
Adrish Ray Chaudhuri , Jadavpur University
pp. 21-28

TLCharts: Armor-plating Harel Statecharts with Temporal Logic Conditions (Abstract)

Doron Drusinsky , Naval Postgraduate School
Man-Tak Shing , Naval Postgraduate School
pp. 29-36
Session 2: Co-Design Tools and Techniques

Improvement of Compiled Instruction Set Simulator by Increasing Flexibility and Reducing Compile Time (Abstract)

Moo-Kyoung Chung , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology
pp. 38-44
Session 3: Poster Presentation

Co-Validation Environment for Memory Card Compatibility Test: A Case Study (Abstract)

Chankin Park , Samsung Electronics Co., Ltd.
Seungmo Cho , Samsung Electronics Co., Ltd.
Jaewook Lee , Samsung Electronics Co., Ltd.
Hyungjun Park , Samsung Electronics Co., Ltd.
pp. 62-65

Rapid Prototyping and Performance Analysis for CDMA2000 (Abstract)

M. De Nobili , University of Strathclyde
R. W. Stewart , University of Strathclyde
G. C. Freeland , EnTegra Ltd.
pp. 70-73

State Pruning for Test Vector Generation for a Multiprocessor Cache Coherence Protocol (Abstract)

Ying Chen , University of Minnesota
Dennis Abts , Cray Inc.
David J. Lilja , University of Minnesota
pp. 74-77
Session 4: System Modeling and Architecture (I)

Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards (Abstract)

Rawat Siripokarpirom , Technical University Hamburg-Harburg
Friedrich Mayer-Lindenberg , Technical University Hamburg-Harburg
pp. 96-102

High Level Synthesis Methodology from C to FPGA Used for a Network Protocol Communication (Abstract)

M. Diaby , University Pierre et Marie Curie
M. Tuna , University Pierre et Marie Curie
J.-L. Desbarbieux , University Pierre et Marie Curie
F. Wajsburt , University Pierre et Marie Curie
pp. 103-108
Keynote Speech
Session 5: Methodologies and Tools

Automatic Generation of Virtual Prototypes (Abstract)

P. Belanović , Vienna University of Technology
M. Holzer , Vienna University of Technology
B. Knerr , Vienna University of Technology
M. Rupp , Vienna University of Technology
G. Sauzon , Infineon Technologies
pp. 114-118

Rapid Software Prototyping Using Visual Language Techniques (Abstract)

Kang Zhang , University of Texas at Dallas
Guang-Lei Song , University of Texas at Dallas
Jun Kong , University of Texas at Dallas
pp. 119-126

Generation of Distributed Programs in Their Target Execution Environment (Abstract)

Jean-Pierre Velu , SAGEM SA
Fabrice Kordon , Université Pierre & Marie Curie
pp. 127-134
Session 6: FPGA-Based Systems (I)

Self-Reconfiguration of Communication Interfaces (Abstract)

André Meisel , Chemnitz University of Technology
Markus Visarius , Chemnitz University of Technology
Wolfram Hardt , Chemnitz University of Technology
Stefan Ihmor , University of Paderborn
pp. 144-150

Multi-User FPGA Co-Simulation over TCP/IP (Abstract)

Daniel Denning , Institute of System Level Integration
James Irvine , Strathclyde University
Derek Stark , Nallatech Ltd
Malachy Devlin , Nallatech Ltd
pp. 151-156

SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation (Abstract)

C. Tanougast , Universit? Henri Poincar? -Nancy 1
Y. Berviller , Universit? Henri Poincar? -Nancy 1
C. Mannino , Universit? Henri Poincar? -Nancy 1
H. Rabah , Universit? Henri Poincar? -Nancy 1
M. Janiaut , Universit? Henri Poincar? -Nancy 1
S. Weber , Universit? Henri Poincar? -Nancy 1
pp. 157-163

Rapid Prototyping of a Co-Designed Java Virtual Machine (Abstract)

Kenneth B. Kent , University of New Brunswick
Hejun Ma , University of New Brunswick
Micaela Serra , University of New Brunswick
pp. 164-171
Session 7: Case Studies

Transmission Systems Prototyping Based on Stateflow/Simulink Models (Abstract)

Nikolaos Papandreou , Research Academic Computer Technology Institute
Maria Varsamou , University of Patras
Theodore Antonakopoulos , University of Patras
pp. 174-179

A Case Study on Rapid Prototyping of Hardware Systems: The Effect of CAD Tool Capabilities, Design Flows, and Design Styles (Abstract)

Apostolos Dollas , Technical University of Crete
Kyprianos Papademetriou , Technical University of Crete
Euripides Sotiriades , Technical University of Crete
Dimitrios Theodoropoulos , Technical University of Crete
Iosif Koidis , Technical University of Crete
George Vernardos , Technical University of Crete
pp. 180-186

Rapid Prototyping of an Integrated Testing and Debugging Unit (Abstract)

Ralf Ludewig , Darmstadt University of Technology
Thomas Hollstein , Darmstadt University of Technology
Falko Schütz , Darmstadt University of Technology
Manfred Glesner , Darmstadt University of Technology
pp. 187-192

Transaction-Level Prototyping of a UMTS Outer-Modem for System-on-Chip Validation and Architecture Exploration (Abstract)

Paolo Martinelli , STMicroelectronics N.V.
Armin Wellig , STMicroelectronics N.V.
Julien Zory , STMicroelectronics N.V.
pp. 193-200
Session 8: System Modeling and Architecture (II)

Modeling and Simulation of System-of-Systems Timing Constraints with UML-RT and OMNeT++ (Abstract)

J. Bret Michael , Naval Postgraduate School
Man-Tak Shing , Naval Postgraduate School
Michael H. Miklaski , Naval Postgraduate School
Joel D. Babbitt , Naval Postgraduate School
pp. 202-209

Abstract RTOS Modeling for Embedded Systems (Abstract)

Fabiano Hessel , Pontif?cia Universidade Cat?lica do RS
Vitor M. da Rosa , Pontif?cia Universidade Cat?lica do RS
Igor M. Reis , Pontif?cia Universidade Cat?lica do RS
Ricardo Planner , Pontif?cia Universidade Cat?lica do RS
C?sar A. M. Marcon , Universidade Federal do Rio Grande do Sul
Altamiro A. Susin , Universidade Federal do Rio Grande do Sul
pp. 210-216

Architecture Exploration of a Large Scale System (Abstract)

Sylvain Alliot , ASTRON, Netherlands Foundation for Research in Astronomy
Ed Deprettere , Leiden University
pp. 217-224
Session 9: FPGA-Based Systems (II)

Implementation of a Channel Equalizer for OFDM Wireless LANs (Abstract)

Mois? Serra , Universitat de Vic
Pere Mart? , Universitat de Vic
Jordi Carrabina , Universitat Aut?noma de Barcelona
pp. 232-238

Prototyping with a Bio-Inspired Reconfigurable Chip (Abstract)

Yann Thoma , Swiss Federal Institute of Technology of Lausanne
Eduardo Sanchez , Swiss Federal Institute of Technology of Lausanne
Carl Hetherington , University of York
Juan-Manuel Moreno , Technical University of Catalunya
pp. 239-246
Author Index

Author Index (PDF)

pp. 247
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