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Rapid System Prototyping, IEEE International Workshop on (2001)
Monterey, California
June 25, 2001 to June 27, 2001
ISBN: 0-7695-1206-2
pp: 0038
Chistophe Bobda , Paderborn University, Heinz Nixdorf Institute
Nils Steenbock , Paderborn University, Heinz Nixdorf Institute
Abstract: The use of FPGAs(Field Programmable Gate Arrays) in the area of rapid prototyping and reconfigurable computing has been successfull in the past [1]. Although many experiments have shown FPGAs to be faster than general purpose processors and more flexible than ASICs(Application Specific Integrated Circuits) on some classes of problems, few experiments have offered a computing platform which exploits the reconfigurability aspect of FPGAs and combine FPGAs and processors to provide better solutions on applications. The goal of this paper is to show through an efficient implementation of the Singular Value Decomposition( SVD) of very large matrices, the possibility of integrating FPGAs as part of a Distributed Reconfigurable System (DRS). A cluster of 8 worstations with two FPGA-boards was built for this purpose. The algorithm is currently running as a pure software solution, but we are working to integrate the FPGAs in the computation. First results are encouraging, showing that the performance of the new platform can be high compare to pure software solutions.
Chistophe Bobda, Nils Steenbock, "Singular Value Decomposition on Distributed Reconfigurable Systems", Rapid System Prototyping, IEEE International Workshop on, vol. 00, no. , pp. 0038, 2001, doi:10.1109/IWRSP.2001.933836
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