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Rapid System Prototyping, IEEE International Workshop on (2000)
Paris, France
June 21, 2000 to June 23, 2000
ISSN: 1074-6005
ISBN: 0-7695-0668-2
TABLE OF CONTENTS

Introduction (PDF)

pp. viii
Session 1: Co-Design Methodologies

Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems (Abstract)

T. Roudier , TIMA Laboratory
A.A. Jerraya , TIMA Laboratory
A. Baghdadi , TIMA Laboratory
W. Cesario , TIMA Laboratory
N-E. Zergainoh , TIMA Laboratory
pp. 8
Session 2: Software Methodologies

A Risk Assessment Model for Software Prototyping Projects (Abstract)

Juan Carlos Nogueira , Naval Postgraduate School
Swapan Bhattacharya , Naval Postgraduate School
Luqi , Naval Postgraduate School
pp. 28

Processor Models for Retargetable Tools (Abstract)

Rajat Moona , Indian Institute of Technology at Kanpur
pp. 34

MODUS: Integrated Behavior-Oriented Model for Rapid Prototyping (Abstract)

Fernando de Cuadra García , Universidad Pontificia Comillas
Yolanda González Arechavala , Universidad Pontificia Comillas
pp. 40

Equivalence Checking of Two Statechart Specifications (Abstract)

Jin-Young Choi , Korea University
Myung-Hwan Park , Korea University
Inhye Kang , Korea University
Ki-Seok Bang , Korea University
pp. 46
Session 3: Tools

Hardware/Software Co-Design of a Java Virtual Machine (Abstract)

Kenneth B. Kent , University of Victoria
Micaela Serra , University of Victoria
pp. 66

Emulator Environment Based on an FPGA Prototyping Board (Abstract)

Sang-yong Yoon , Seoul National University
Soo-Ik Chae , Seoul National University
Kyung-soo Oh , Daewoo Electronics Co. Ltd
pp. 72

A Comprehensive Prototyping-Platform for Hardware-Software Codesign (Abstract)

Andreas Koch , Technical University of Braunschweig
pp. 78
Session 4: Real Time Systems

Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems (Abstract)

Shuvra S. Bhattacharyya , University of Maryland at College Park
Bishnupriya Bhattacharya , University of Maryland at College Park
pp. 84
Session 5: Hardware Methodologies

Speeding Up Hardware Prototyping by Incremental Simulation/Emulation (Abstract)

N. CaÑellas , Universitat Rovira i Virgili
J.M. Moreno , Universitat Polit?cnica de Catalunya
pp. 98

A Prototype of an AAL for High Bit Rate Real-Time Data Transmission System over ATM Networks Using a RSE CODEC (Abstract)

Helmut Steckenbiller , Fraunhofer Institute for Communication Systems
Arnold Plankl , Fraunhofer Institute for Communication Systems
Dirk Eilers , Fraunhofer Institute for Communication Systems
Rudi Knorr , Fraunhofer Institute for Communication Systems
Alfred Voglgsang , Fraunhofer Institute for Communication Systems
Gerri Körner , Fraunhofer Institute for Communication Systems
pp. 109

The FLYSIG Prototyping Approach (Abstract)

Wolfram Hardt , University of Paderborn
pp. 115
Session 6: Code Generation

A Verilog to C Compiler (Abstract)

D.J. Greaves , University of Cambridge
pp. 122

Using MetaScribe to Prototype an UML to C++/Ada95 Code Generator (Abstract)

Fabrice Kordon , Université Pierre & Marie Curie
Dan Marius Regep , CS TELECOM
pp. 128

An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-Specifications (Abstract)

Georg Färber , Technische Universit?t M?nchen
Annette Muth , Technische Universit?t M?nchen
Thomas Kolloch , Technische Universit?t M?nchen
Thomas Maier-Komor , Technische Universit?t M?nchen
pp. 134
Session 7: Methodologies

Integration and Evolution of Model-Based Tool Prototypes (Abstract)

Ansgar Bredenfeld , GMD-Institute for Autonomous intelligent Systems (AiS)
pp. 142

Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded System (Abstract)

Juergen Becker , Darmstadt University of Technology
Manfred Glesner , Darmstadt University of Technology
Frank-Michael Renner , Darmstadt University of Technology
pp. 154

Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications (Abstract)

Lukusa Kabulepa , Darmstadt University of Technology
Jiirgen Becker , Darmstadt University of Technology
Manfred Glesner , Darmstadt University of Technology
Frank-Michael Renner , Darmstadt University of Technology
pp. 160
Session 8: Reconfigurability in Hardware Systems

Reconfigurable Instruction Set Processors: A Survey (Abstract)

Francisco Barat , Katholieke Universiteit Leuven
Rudy Lauwereins , Katholieke Universiteit Leuven
pp. 168

Highly Configurable Control Boards: A Tool and a Design Experience (Abstract)

T. Riesgo , Universidad Polit?cnica de Madrid
J. Uceda , Universidad Polit?cnica de Madrid
E. de la Torre , Universidad Polit?cnica de Madrid
E. Macip , INDRA DTD
M. Rizzi , INDRA DTD
pp. 174
Session 9: Hardware Systems

Power-Constrained Block-Test List Scheduling (Abstract)

Xiaojun Wang , Dublin City University
Valentina Muresan , Universitatea Politehnica Timisoara
Valentin Muresan , Dublin City University
Mircea Vladutiu , Universitatea Politehnica Timisoara
pp. 182

Adaptive FPGA Placement by Natural Optimization (Abstract)

Román Hermida , University Complutense de Madrid
Juan de Vicente , E.T.S.I.A.N
Juan Lanchares , University Complutense de Madrid
pp. 188

FPGA Technology Snapshot: Current Devices and Design Tools (Abstract)

Helena Krupnova , Institut National Polytechnique de Grenoble
Gabriele Saucier , Institut National Polytechnique de Grenoble
pp. 200
Session 11: Methodologies

Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams (Abstract)

Manfred Glesner , Darmstadt University of Technology
Ulrich Mayer , Darmstadt University of Technology
pp. 214
Session 12: Embedded Systems

Efficient Clock-Cycle Precise Simulation at Architecture Level in C++ (Abstract)

Hans Christoph Zeidler , Universit?t der Bundeswehr Hamburg
Göran Eggers , Universit?t der Bundeswehr Hamburg
pp. 222

Embedded System Architecture Design Based on Real-Time Emulation (Abstract)

Wolfgang Rosenstiel , University of T?bingen
Carsten Nitsch , Forschungszentrum Informatik
Dr. Karlheinz Weiss , Forschungszentrum Informatik
Thorsten Steckstor , Forschungszentrum Informatik
pp. 228

Author Index (PDF)

pp. 234
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