The Community for Technology Leaders
Reconfigurable Computing and FPGAs, International Conference on (2011)
Cancun, Quintana Roo Mexico
Nov. 30, 2011 to Dec. 2, 2011
ISBN: 978-0-7695-4551-6
pp: 386-391
This paper presents an offline tool-chain which automatically extracts loops (Mega blocks) from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit (RPU) for those loops. The system moves loops from the CPU to the RPU transparently, at runtime, and without changing the executable binaries. The system was implemented in an FPGA and for the tested kernels measured speedups ranged between 3.9x and 18.2x for a Micro Blaze CPU without cache. We estimate speedups from 1.03x to 2.01x, when comparing to the best estimated performance achieved with a single Micro Blaze.
Reconfigurable Computing, Graph Mapping, Binary Translation, Megablock, Hardware Accelerator, Instruction Trace
João M.P. Cardoso, Nuno Paulino, João Canas Ferreira, João Bispo, "From Instruction Traces to Specialized Reconfigurable Arrays", Reconfigurable Computing and FPGAs, International Conference on, vol. 00, no. , pp. 386-391, 2011, doi:10.1109/ReConFig.2011.43
155 ms
(Ver 3.3 (11022016))