Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism
Reconfigurable Computing and FPGAs, International Conference on (2010)
Cancun, Quintana Roo Mexico
Dec. 13, 2010 to Dec. 15, 2010
In this paper we propose a strategy for better exploiting Multi-Processor Systems-on-Chip resources utilization by means of using a control-loop feedback mechanism. We apply the proposed techniques in a purely distributed memory MPSoC architecture that is composed of a frequency scaling module responsible for tuning the frequency of processors at run-time. Results show very promising in terms of adaptation capabilities for system with dynamic workload. Performance results demonstrate the effectiveness of the proposed approach when workload requirements for applications may vary, affecting the overall performance of the system. For validating the proposed approach we have implemented a multi-thread MJPEG decoder application and created an architecture model with/without perturbations in the system.
MPSoC, homogeneous, PID, adaptive, NoC, distributed memory, RTOS
Nicolas Hebert, Gabriel Marchesan Almeida, Michel Robert, Lionel Torres, Sameer Varyani, Gilles Sassatelli, Rémi Busseuil, Pascal Benoit, "Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism", Reconfigurable Computing and FPGAs, International Conference on, vol. 00, no. , pp. 382-387, 2010, doi:10.1109/ReConFig.2010.17